Transcript Lecture 5

ECE 232
Hardware Organization and Design
Lecture 5
MIPS Assembly Instructions
Maciej Ciesielski
www.ecs.umass.edu/ece/labs/vlsicad/ece232/spr2002/index_232.html
ECE 232 L5 Assembl.1
Adapted from Patterson 97 ©UCB
Copyright 1998 Morgan Kaufmann Publishers
Outline
° Classes of instructions, formats
• R-type (register-register)
• I-type (immediate)
• J-type (jump)
° MIPS assembly instructions
•
•
•
•
•
Register access – operand(s) in registers
Constant operands (immediate)
Array access - operand in memory A[k]
Making decisions (if then else)
Branching further away
° Pseudo instructions
ECE 232 L5 Assembl.2
Adapted from Patterson 97 ©UCB
Copyright 1998 Morgan Kaufmann Publishers
MIPS R3000 Instruction Set Architecture
Registers
° Instruction Categories
•
•
•
•
•
•
Load/Store
Computational
Jump and Branch
Floating Point
- coprocessor
Memory Management
Special
R0 - R31
PC
HI
LO
3 Instruction formats: all 32-bit wide
R-type
OP
rs
rt
I-type
OP
rs
rt
J-type
OP
ECE 232 L5 Assembl.3
rd
shft
funct
immediate
jump target
Adapted from Patterson 97 ©UCB
Copyright 1998 Morgan Kaufmann Publishers
Register Instructions
° Assume: g, h, i, j are stored in registers $s1 - $s4.
Result f to be stored in $s0.
° Compile: f = (g + h) – (i + j)
into MIPS instructions:
add $t0, $s1, $s2
# register $t0  (g+h)
add $t1, $s3, $s4
# $t1  (i + j)
sub $s0, $t0, $t1
# $s0  $t0 - $t1
R-type
ECE 232 L5 Assembl.4
OP
rs
rt
Adapted from Patterson 97 ©UCB
rd
shft
funct
Copyright 1998 Morgan Kaufmann Publishers
Immediate format
° Immediate = small constant stored in the instruction
addi $sp, $sp, const
6
OP
I-type
5
rs
5
rt
° Range of constant operand:
# $sp  $sp + const
16
const
const  216-1
° Set on less-then, immediate
slti $t0, $s2, const # $t0  1 if $s2 < const
ECE 232 L5 Assembl.5
Adapted from Patterson 97 ©UCB
Copyright 1998 Morgan Kaufmann Publishers
Operand in memory
° Let A[ ] = array whose starting (base) address is in $s3;
let variable h be associated with register $s2;
° Compile: A[5] = h + A[8]
8*4 = 32 bytes
(byte-addressable)
into MIPS instructions:
lw
# $t0  A[8]
$t0, 32 ($s3)
add $t0, $s2, $t0
# $t0  h+$t0
sw $t0, 20 ($s3)
# A[5]  $t0
$s3
5*4 = 20
I-type
ECE 232 L5 Assembl.6
OP
rs
rt
Adapted from Patterson 97 ©UCB
immediate
Copyright 1998 Morgan Kaufmann Publishers
8
7
6
5
4
3
2
1
Array with variable index
° A[ ] = array with base address in $s3;
variables g, h, i associated with registers $s1, $s2, $s4
° Compile: g = h + A[i]
into MIPS instructions:
add $t1, $s4, $s4
# $t1  i+i = 2i
add $t1, $t1, $t1
# $t1  2i+2i = 4i
add $t1, $t1, $s3
lw $t0, 0 ($t1)
add $s1, $s2, $t0
# $t1  address of A[i]
# $t0  A[i]
# $s1  h + A[i]
ECE 232 L5 Assembl.7
Adapted from Patterson 97 ©UCB
Copyright 1998 Morgan Kaufmann Publishers
If statements
° Let variables f, g, h, i, j be associated with $s0 - $s4
° Compile:
if (i == j) go to L1;
f = g + h;
L1:
f = f – i;
into MIPS instructions:
L1:
beq $s3, $s4, L1
# if i = j, go to L1
add $s0, $s1, $s2
sub $s0, $s0, $s3
# f = g + h (skipped if i=j)
# f = f – i (always executed)
ECE 232 L5 Assembl.8
Adapted from Patterson 97 ©UCB
Copyright 1998 Morgan Kaufmann Publishers
Jump instructions
° Regular jump uses J-format
j Label
J-type
# jump to Label
26
Label = jump target
OP
° jr (jump on register address) uses R-format
jr $t1
R-type
OP
# jump to A[($t1)]
rs
0
0
0
funct
OP/funct = jr
ECE 232 L5 Assembl.9
Adapted from Patterson 97 ©UCB
Copyright 1998 Morgan Kaufmann Publishers
If then else statements
° Let variables f, g, h, i, j be associated with $s0 - $s4
° Compile:
if (i == j) f = g + h; else f = g –h;
into MIPS instructions:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit:
J-type
ECE 232 L5 Assembl.10
# if i  j, go to Else
# f = g + h (skipped if i  j)
# go to Exit
# f = g – h (skipped if i = j)
OP
Adapted from Patterson 97 ©UCB
jump target
Copyright 1998 Morgan Kaufmann Publishers
Pseudo-instructions
° Let variables a, b be associated with $s0, $s1
° Compile:
if (a < b) go to L
into MIPS instructions:
slt $t0, $s0, $s1
bne $t0, $zero, L
# $t0  1 if $s0 < $s1 (a < b)
# if $t0  0, go to L
° We can create pseudo-instruction: blt $s0, $s1, L
° Special registers, useful in beq, bne, slt:
° $zero is a special register, holds 0
° $at is another special register (1-bit) used in slt
(set $at on less-then)
ECE 232 L5 Assembl.11
Adapted from Patterson 97 ©UCB
Copyright 1998 Morgan Kaufmann Publishers
Branching further away – pseudo-instruction
small constant ( 216-1)
° Consider a branch instruction
beq $s0, $s1, L1
I-type
# branch to L1 if $s0=$s1
6
5
5
16
OP
rs
rt
immediate
° Change, to offer greater branching distance ( 226-1):
pseudo-instruction:
beq $s0, $s1, Large
bne $s0, $s1, L2 # branch to L2 if $s0 $s1
j Large
# unconditional jump to “Large”
L2:
6
J-type
ECE 232 L5 Assembl.12
OP
26
Large – jump target
Adapted from Patterson 97 ©UCB
Copyright 1998 Morgan Kaufmann Publishers
Loading large numbers
° Instruction lui: load upper immediate
# $t0[31:16]  const
lui $t0, const
6
OP
I-type
5
0
5
16
const
rt
16
$to:
const
31
ECE 232 L5 Assembl.13
16
0000 0000 0000 0000
16 15
Adapted from Patterson 97 ©UCB
0
Copyright 1998 Morgan Kaufmann Publishers
MIPS Addressing Modes/Instruction Formats
All instructions are 32-bit wide
• Register (direct)
op
rs
rt
rd
register
• Immediate
op
rs
rt
immed
• Base+index
op
rs
rt
immed
+
register
• PC-relative
op
rs
rt
PC
ECE 232 L5 Assembl.14
Adapted from Patterson 97 ©UCB
Memory
immed
Memory
+
Copyright 1998 Morgan Kaufmann Publishers
Operation Summary
Support these simple instructions, since they
will dominate the number of instructions executed:
load, store,
add, subtract,
move register-register,
and,
shift,
compare equal, compare not equal,
branch,
jump,
call,
return;
ECE 232 L5 Assembl.15
Adapted from Patterson 97 ©UCB
Copyright 1998 Morgan Kaufmann Publishers