Transcript Lecture 4

CSE243: Introduction to Computer Architecture and
Hardware/Software Interface
Topics covered:
68000 Instruction Set Architecture
68000 Instruction Set Architecture
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Registers and addressing
Addressing modes
Instructions
Assembly language
Branch instructions
Stacks and subroutines
Simple programs in 68000 assembly language
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Registers and addressing
 External word length:
Word length used to transfer data between the processor and
memory.
 16 bits.
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 Internal word length:
Refers to the size of the processor registers
 32 bits.
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Register structure
 8 data registers (D0-D7) and 8 address registers (A0-A7):
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Each is 32 bits long.
 Instructions use operands of three different lengths:
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Long word – 32 bits
Word – 16 bits
Byte – 8 bits
 A byte or a word operand stored in a data register is in the
low order bit positions of a register:
Most instructions operating on byte or word operands do not
affect the higher order bit positions.
 Some instructions extend the sign of a shorter operand into
the high-order bits.
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Register structure (contd..)
 Address registers hold information used in determining the
addresses of memory operands:
Address and data registers can also be used as index registers.
 Address register A7 has a special function of serving as the
processor stack pointer.
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 Address registers and calculations involve 32 bits:
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Only the least 24 significant bits of an address are used
externally to access the memory.
 Processor Status Register (SR):
Five condition code bits.
 Three interrupt bits (function will be clear when we discuss
I/0)
 Two mode-select bits.
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Register structure (contd..)
Long word
Word
Byte
31
16 15
8 7
0
D0
D1
D2
D3
D4
User stack pointer
A7
Stack
pointers
Supervisor stack pointer
Data
registers
PC
D5
15 13 10 8
D6
SR
T - Trace mode select
S - Supervisor mode select
I - Interrupt mask
D7
A0
4
0
Status register
CVZN-
Carry
Overflow
Zero
Negative
A1
A2
A3
Address
registers
A4
A5
A6
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Addressing
Word
addresses
Contents
0
byte 0
byte 1
2
byte 2
byte 3
i
byte i
byte i+1
i+2
byte i+2
byte i+3
224 - 2
byte 224 - 2
byte 224 - 1
Long word 0
Long word i
•Byte addressable memory
•Memory is organized in 16-bit words.
•Two consecutive 16-bit words constitute
one 32-bit long word.
•Word address must be an even number,
that is, words must be aligned on an
even boundary.
•Byte in the high-order position has the
same address as the word, the byte in
the low-order position has the next
higher address. This is the big endian
address assignment.
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Addressing (contd..)
 68000 generates 24-bit memory addresses.
 Addressable space is 224 (16,777,216 or 16M) bytes.
 Addressable space may be thought of as consisting of:
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512 (29) pages of 32K (215) bytes each.
Page 0 is hexadecimal addresses 0 to 7FFF.
Page 1 is hexadecimal addresses 8000 to FFFF.
Last page is hexadecimal addresses FF8000 to FFFFF.
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Addressing modes
 Instruction size:
Many instructions are one word (16-bit long), some require
additional 16-bit words for extra addressing information.
 First word of an instruction is the OP-code word.
 Subsequent words (if any) are called extension words.
 Note that the 68000 does not place a one word limit on the
instruction size, it is a CISC architecture.
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 Immediate mode
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Operand is included in the instruction.
Byte, word, long-word operands are specified in the extension
word.
Some very small operands are included in the OP-code word.
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Addressing modes (contd..)
 Absolute mode:
Absolute address of an operand is given in the extension word.
 Long mode: 24-bit address is specified.
 Short mode: 16-bit value is specified, which serves as the loworder 16 bits of an address.
• Sign bit of the 16-bit value is extended to provide the highorder 8 bits.
• Sign-bit is 0 or 1, so two pages can be addressed: 0, and
FF8.
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 Register mode:
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Operand is in a processor register specified in the instruction.
 Register indirect mode:
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Effective address (EA) of an operand is in a processor register
which is specified in an instruction.
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Addressing modes (contd..)
 Autoincrement mode:
EA is in one of the address registers which is specified in the
instruction.
 After the operand is addressed, the contents of the address
register are incremented by 1 (byte), 2 (word), 4 (long-word).
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 Autodecrement mode:
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Same as above, except the contents are decremented before
the operand is accessed.
 Basic index mode:
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16-bit signed offset and an address register are specified.
 Full index mode:
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8-bit signed offset, an address register and an index register
(either a data or address register) are specified.
 Basic relative and Full relative modes:
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Same as Basic index and Full index modes respectively, except
PC is used instead of address register.
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Addressing modes (contd..)
1000
OP-code word
1002
Extension word
100 = offset
1102
1104
6 = index
1106
1108
Operand
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A1
•Consider the instruction:
ADD 100(PC,A1), D0
•Full relative mode for the source operand.
•Register mode for the destination operand.
•Compute the EA of the source operand:
- Suppose A1 holds the value 6.
- Suppose the OP-code word is at 1000.
Array
- After the OP-code word is fetched, PC
points to the extension word, i.e. 1002.
EA = [PC] + [A1] + 100
Thus, EA is 1108.
•This could be used to address the data in an
array form.
•In relative modes, PC need not be specified
explicitly in the instruction.
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Instructions
 Extensive set of instructions.
 Both two-operand and one-operand instructions.
 Two-operand instructions:
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Format: OP src, dst.
Assembly language notation, the actual encoding may not be in
the same order.
OP specifies the operation performed.
Result is placed in the destination location.
For most two operand instructions, either src, or dst operand
must be in a data register. Other operand may be specified
using any one of the addressing modes.
The only two operand instruction where any addressing mode
may be used to specify both the operands is the MOVE
instruction.
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Instructions (contd..)
Consider the instruction: ADD #9, D3
Add 9 to contents of D3 and store result in D3.
15 12 11 9 8 7 6 5
1 1 01 dst 0
0
src
size
operation
Binary
Hex
1 1 0 10 1 1 00 1 1 11 1 0 0
D
6
7
C
•Bits 15-12 and 8 specify the operation.
•Bits 9-11 specify the destination register D3.
•Bits 7-5 specify the size of the operands, default is
word, with a bit pattern 01.
•Bits 5-0 identifies that the source operand is immediate
with the pattern 111100.
•The actual value of the source operand is in the extension
word.
•Binary and hex encoding of the OP-code word are
shown.
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Instructions (contd..)
Consider the instruction: ADD #9, D3
Add 9 to contents of D3 and store result in D3.
i
D67C
i +2
OP-code word
9
Immediate operand
i +4
D3
25
D3
34
PC
i
PC
i+4
Before
instruction fetch
After
instruction execution
•OP-code word is at location i.
•Operand 9 is in the extension
word at location i+2.
•After the OP-code word is fetched
PC points to i+2.
•After the extension word is
fetched, PC points to i+4.
•Contents of D3 before execution
are 25, and after execution are 34.
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Assembly language
 Instructions can operate on operands of three sizes, size of
the operands must be indicated:
Size of the operand is indicated in the operation mnemonic,
using L for long-word, W for word, and B for byte.
 ADD.L indicates ADD operation with operand size long-word.
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 Representation of numbers:
Default representation is in the decimal form.
 Prefix $ is used for hexadecimal, and % for binary.
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 Representation of Alphanumeric characters:
Placed within quotes, replaced by the assembler with their
ASCII codes.
 Several characters may be placed in a string between quotes.
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Assembler directives
 ORG: Starting address of an instruction or data block.
 EQU: Equating names with numerical values
 DC (Define Constant): Data constants.
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Size indicator may be appended to specify the size of the data
constants. DC.B, DC.W, DC.L.
 DS (Define Storage): Reserve a block of memory.
 Names can be associated with memory locations using labels
as described earlier.
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Condition code flags
 Five condition code flags, stored in the status register.
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N
Z
V
C
X – Extend flag, set the same way as C flag, but not affected
by many instructions. Useful for precision arithmetic.
 Since operands can be of three sizes (byte, word and longword):
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C and X flags depend on the carry-out from bit positions 7, 15
and 31.
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Branch instructions
 Recall that a conditional branch instruction causes program
execution to continue with the instruction at the branch
target address if the condition is met, else the instruction
immediately following the branch is executed.
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Branch target address is computed by adding an offset to the
PC.
 Branch instructions with two types of offset, 8 and 16 bit.
 Branch instructions with 8-bit offset:
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Offset is included in the OP-code word.
Branch target address is within –127 to 128 of the value in PC.
PC contents are incremented at each fetch, offset defines the
distance from the word that follows the branch instruction OPcode word.
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Branch instructions (contd..)
 Branch instructions with a 16-bit offset:
Offset is specified in an extension word following the OP-code
word.
 Branch target address can be in the range of +32K to –32K
from the value in PC.
 Offset is the distance from the extension word to the branch
target.
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 16 conditional branch instructions, each with two offsets.
 1 unconditional branch instruction.
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Stacks and subroutines
 Stack can be implemented using any of the address
registers, with the help of autoincrement and
autodecrement addressing modes.
 Register A7 is designated as the processor stack pointer,
and it points to the processor stack.
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Stack used by the processor for all operations that it performs
automatically, such as subroutine linkage.
 Two different stack pointer registers, for two modes of
operation:
Supervisor mode: All machine instructions can be executed.
 User mode: Certain privileged instructions cannot be executed.
 Application programs: user mode.
 System software: supervisor mode.
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Stacks and subroutines (contd..)
 Stack may be used for:
Subroutine linkage mechanism.
 Passing parameters to a subroutine and returning result from
the subroutine.
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 Branch-to-Subroutine (BSR) is used to call a subroutine:
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Causes the contents of the PC to be pushed onto the stack.
 Return from Subroutine (RTS) is used to return from a
subroutine:
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Causes the return address at the top of the stack to be popped
into the PC.
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Simple programs in 68000 assembly language.
Add the contents of memory locations A and B, and place the result in C.
Size of operands A and B is word.
Recall that:
- For a two-operand instruction, one of the operands has to be placed in a
data register D0 through D7.
MOVE A, D0
ADD B, D0
MOVE D0, C
Move A to register D0.
Add the contents of location B to D0 and store the
result in D0.
Transfer the result in register D to location C.
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Simple programs in 68000 assembly language.
A = 201150
63910
B = 201152
- 21510
201200
OP-code word
201202
20
201204
1150
201206
OP-code word
201208
20
20120A
1152
20120C
OP-code word
20120E
20
201210
2200
•Add the contents of A and B,
and place the result in location
MOVE A,D0 C.
•Size of the operands at locations
A and B is 16 bits.
•A, B, and C and the program
ADD B,D0 to add is stored in the memory
MOVE D0,C
C = 202200
After execution, [202200] = 424
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Simple programs in 68000 assembly language
Program to add A and B, and store the result in C with assembler directives.
Memory
address
label
Assemblerdirectives
C
A
B
Statemen
ts that
generatemachine
instructions
Assemblerdirective
Operation
EQU
ORG
DC.W
DC.W
ORG
MOVE
ADD
MOVE
END
Addressing
or data
information
$202200
$201150
639
– 215
$201200
A,D0
B,D0
D0,C
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Simple programs in 68000 assembly language.
Add N numbers:
- The first number is stored at the starting address NUM1.
- The count of entries to be added is stored at address N.
- Store the result at location SUM.
- Size of each number to be added is Word.
LOOP
MOVE.L
N,D1
MOVEA.L
#NUM1,A2
CLR.L
ADD.W
SUBQ.L
BGT
MOVE.L
D0
(A2)+,D0
#1,D1
LOOP
D0,SUM
N contains n, the number of entries
to be added, and D1 is usedas
a counter that determineshow
many times to executethe loop.
A2 is usedas a pointer to the list entries.
It is initialized to NUM1, the address
of the first entry .
D0 is used to accumulate the sum.
Successiv
e numbers are added in D0.
Decremen
t the counter.
If [D1]> 0, executethe loop again.
Store the sum in SUM.
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