Transcript EECC250 - Shaaban

Estimation of Assembly Programs
Execution Time
• For a CPU running at a constant clock rate:
clock rate = 1 / clock cycle time
• Every machine or assembly instruction takes one or more clock
cycles to complete.
• The total time an assembly program requires to run is given by:
Execution time = Total number of cycles X Clock cycle time
= Instruction count X cycles per instruction X clock cycle time
= Instruction count X cycles per instruction / clock rate
Example:
For a CPU running at 8MHZ is executing a program with a total of 100
000 instructions. Assuming that each instruction takes 10 clock cycles
to complete:
Execution time = 100 000 X 10 / 8 000 000 = 0.125 seconds
EECC250 - Shaaban
#1 lec #16 Winter99 1-24-2000
68000 Cycles Per Instruction
• For the 68000, the number of clock cycles required by
an instruction to execute depends on:
– The exact type of the instruction in question.
– Addressing modes used for both the instruction source
and destination if applicable.
– Size of operands:
• Byte- and word-sized operands usually take the same
number of cycles to process.
• Instructions with long word-sized operands take more cycles
than that with byte/word-sized operands.
• For a 68000 running at 8MHZ all instruction times are
rounded to multiples of four (i.e. 10 becomes 12 etc.).
EECC250 - Shaaban
#2 lec #16 Winter99 1-24-2000
68000 Instructions Summary
Instr
ABCD
ADD
AND
ASL
ASR
Bcc
BCHG
BCLR
BRA
BSET
BSR
BTST
CHK
CLR
CMP
DBcc
DIVS
DIVU
EOR
EXG
EXT
JMP
JSR
LEA
LINK
LSL
LSR
Description
Add decimal with extend
Add
Logical AND
Arithmetic shift left
Arithmetic shift right
Branch conditionally
Bit test and change
Bit test and clear
Branch always
Bit test and set
Branch to subroutine
Bit test
Check register against bounds
Clear operand
Compare
Decrement and branch
conditionally
Signed divide
Unsigned divide
Exclusive OR
Exchange registers
Sign extend
Jump
Jump to subroutine
Load Effective Address
Link stack
Logical shift left
Logical shift right
Instr
MOVE
MULS
MULU
NBCD
NEG
NOP
NOT
OR
PEA
RESET
ROL
ROR
ROXL
ROXR
RTD
RTE
Description
Move source to destination
Signed multiply
Unsigned multiply
Negate Decimal with Extend
Negate
No operation
Ones complement
Logical OR
Push effective address on stack
Reset External devices
Rotate left without extend
Rotate right without extend
Rotate left with extend
Rotate right with extend
Return and deallocate
Return from exception
RTR
RTS
SBCD
Scc
STOP
SUB
SWAP
TAS
TRAP
TRAPV
TST
Return and restore
Return from subroutine
Subtract decimal with extend
Set conditional
Stop
Subtract
Swap data register halves
Test and set operand
Trap
Trap on overflow
Test
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68000 Cycles For MOVE Instructions
Operand Size
Addressing Mode
Clock Cycles
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Time to Calculate Effective Addresses
Addressing Mode
.b.w/.l
(an) (an)+
4/8
4/8
-(an)
6/10
d(an)
8/12
d(an,dn)
10/14
Operand Size
Addressing Mode
.b.w/.l
abs.s
8/12
abs.l
12/16
d(pc)
8/12
d(pc,dn)
10/14
Imm
4/8
Operand Size
The time taken to calculate the effective
address must be added to instructions that
affect a memory address.
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68000 Cycles For Standard Instructions
Operand Size
.b.w/.l
add
and
cmp
divs
divu
eor
muls
mulu
or
sub
Addressing Mode
ea,an
8/6(8)
6/6
8/6(8)
ea,dn
4/6(8)
4/6(8)
4/6
158max
140max
4/8
70max
70max
4/6(8)
4/6(8)
dn,mem
8/12
8/12
8/12
8/12
8/12
(8) time if effective
address is direct
Add effective address
times from above
for mem addresses
Clock Cycles
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Cycles For Immediate Instructions
Operand Size
.b.w/.l
addi
addq
andi
cmpi
eori
moveq
ori
subi
subq
Addressing Mode
#,dn
8/16
4/8
8/16
8/14
8/16
4
8/16
8/16
4/8
#,an
8/8
8/14
8/8
#,mem
12/20
8/12
12/20
8/12
12/20
12/20
12/20
8/12
Moveq.l only
nbcd+tas.b only
scc false/true
Add effective address
times from above
for mem addresses
Clock Cycles
EECC250 - Shaaban
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Cycles for Single-Operand Instructions
Operand Size
.b.w/.l #,dn
clr
4/6
nbcd
6
neg
4/6
negx
4/6
not
4/6
scc
4/6
tas
4
tst
4/4
Addressing Mode
#,an
4/6
6
4/6
4/6
4/6
4/6
4
4/4
#,mem
8/12
8
8/12
8/12
8/12
8/8
10
4/4
Add effective address
times from above
for mem addresses
Clock Cycles
EECC250 - Shaaban
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Cycles for Shift/Rotate Instructions
Operand Size
.b.w/.l
asr,asl
lsr,lsl
ror,rol
roxr,roxl
Addressing Mode
dn
6/8
6/8
6/8
6/8
an
6/8
6/8
6/8
6/8
mem
8
8
8
8
Clock Cycles
Memory is byte only
For register add 2x
the shift count
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Misc. Instructions
Addressing Mode
jmp
jsr
lea
pea
(an)
8
16
4
12
movem t=4
m>r
12
movem t=5
r>m
8
movem
movem
(an)+
-
d(an
d(pc
-(an) d(an) ,dn) abs.s abs.l d(pc) ,dn)
10
14
10
12
10
14
18
22
18
20
18
22
8
12
8
12
8
12
16
20
16
20
16
20
12
-
16
18
16
20
16
18
-
8
12
14
12
16
-
-
add t x number of registers for .w
add 2t x number of registers for .l
Clock Cycles
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Cycles for Bit Manipulation Instructions
Operand Size
.b/.l
bchg
bclr
bset
btst
Addressing Mode
register .l
only
8/12
10/14
8/12
6/10
memory .b
only
8/12
8/12
8/12
4/8
Clock Cycles
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Cycles To Process Exceptions
Address Error
Bus Error
Interrupt
Illegal Instr.
Privilege Viol.
Trace
50
50
44
34
34
34
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Operand Size
.b.w/.l
addx
cmpm
subx
abcd
sbcd
Bcc
bra
bsr
DBcc
chk
trap
trapv
Cycles for Other Instructions
dn,dn
4/8
4/8
6
6
.b/.w
.b/.w
.b/.w
t/f
-
m,m Addressing Mode
Add effective address
18/30
times from above
12/20
for mem addresses
18/30
18
.b only
18
.b only
10/10
8/12
10/10
18/18
10
12/14
40 max
8
34
34
4
Clock Cycles
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Cycles for Other Instructions
reg<>mem
movep
.w/.l
16/24
Addressing Mode
andi
andi
eori
eori
exg
ext
link
move
move
move
move
to
to
to
to
ccr
sr
ccr
sr
to ccr
to sr
from sr
to usp
Reg
20
20
20
20
6
4
18
12
12
6
4
Mem
12
12
8
-
Clock Cycles
Addressing Mode
move from usp
nop
ori to ccr
ori to sr
reset
rte
rtr
rts
stop
swap
unlk
Reg
4
4
20
20
132
20
20
16
4
4
12
EECC250 - Shaaban
#14 lec #16 Winter99 1-24-2000
Timing Example 1
Instruction
RANDOM
ADDI.B
LSL.B
NOT.B
RTS
Clock Cycles
#17,D0
#3,D0
D0
Total Cycles needed:
8
12
4
16
40 cycles
For a 68000 running at 8MHZ:
Clock cycle = 125 nsec
Execution time = 40 X 125 nsec = 5 ms = 5 x 10-6 second
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Timing Example 2
Clock Cycles
READ
Instruction
MOVE.B
ADD.W
SUBQ.B
BNE
#255,D0
(A0)+,D1
#1,D0
READ
Overhead
8
Loop
8
4
10
Total Cycles Needed = 8 + 255 (8 + 4 + 10)
= 8 + 255 x 22
= 5618 cycles
Execution time for 8MHZ 68000 = 5618 x 125 nsec
= 0.00070225 Seconds = .702 msec
EECC250 - Shaaban
#16 lec #16 Winter99 1-24-2000
Timing Example 3
•
TOBIN converts a four-digit BCD number in the lower word of D0 into a
binary number returned in D2
Clock Cycles
overhead
outer
loop
Instructions
TOBIN
NEXTDIGIT
GETNUM
CLR.L
MOVEQ
MOVEQ
CLR.W
LSL.W
ROXL.W
DBRA
MULU
ADD.W
DBRA
RTS
D2
#3,D6
#3,D5
D1
#1,D0
#1,D1
D5,GETNUM
#10,D2
D1,D2
D6,NEXTDIGIT
inner
loop
6
4
4
4
8
8
10
42
4
10
16
Total Clock cycles = overhead + ( (inner loop cycles x 4 ) + outer loop cycles) x 4
= 26
+ ( ( 26 x 4 ) + 64 ) x 4
=
26
+ 168 x 4 = 698 cycles
= 698 x 125 nsec = 87.25 ms
or over 11 400 BCD numbers converted to binary every second.
EECC250 - Shaaban
#17 lec #16 Winter99 1-24-2000