Transcript Slide 1
Computer Organization & Assembly Language Instruction Execution Interrupts Instruction Cycle Fetch 1. 2. 3. Fetch an instruction from memory Decode the instruction to determine the operation Fetch data from memory if necessary Execute 4. 5. 2 Perform the operation on the data Store the result in memory if needed Contd.. Internal CPU Registers: 3 Program Counter (PC) = Address of instruction Instruction Register (IR) = Instruction being executed Accumulator (AC) = Temporary Storage Contd.. Fetch the instruction from the memory Address in the Program Counter register Program Counter (PC) holds address of next instruction to fetch Increment the Program Counter Unless told otherwise Instruction loaded into Instruction Register (IR) Decode the type of instruction Fetch the operands Execute the instruction Store the results 4 Example Program Execution 5 Instruction Execution Cycle Program (RAM) PC I-1 I-2 I-3 I-4 fetch Data (RAM) op1 op2 registers I-1 Instruction Queue decode ALU execute store the output 6 Instruction Cycle State Diagram 7 Interrupts Changing Program Flow 8 Interrupts Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program Timer Generated by internal processor timer Used in pre-emptive multi-tasking I/O e.g. overflow, division by zero from I/O controller Hardware failure 9 e.g. memory parity error Interrupt Cycle Added to instruction cycle Processor checks for interrupt Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending: 10 Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program Transfer of Control via Interrupts 11 Instruction Cycle with Interrupts 12 Instruction Cycle (with Interrupts) - State Diagram 13 Multiple Interrupts Disable interrupts Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur Define priorities 14 Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt Multiple Interrupts - Sequential 15 Multiple Interrupts – Nested 16 Program Flow Control 17 References Chapter 1, Ytha Yu and Charles Marut, “Assembly Language Programming and Organization of IBM PC” Chapter 3,William Stallings,“Computer Organization & Architecture” 18