Transcript Document

Dec
14
Hex
E
Bin
00001110
ORG ; FOURTEEN
Interrupts
In x86 PC
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
OBJECTIVES
this chapter enables the student to:
• Explain how the x86 executes interrupts by using
the interrupt vector table and interrupt routines.
• List the differences between interrupts and
CALL instructions.
• Describe the differences between hardware
and software interrupts.
• Examine the ISR for any interrupt, given its
interrupt number.
• Describe the function of each pin of the 8259
programmable interrupt controller (PIC) chip.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
OBJECTIVES
this chapter enables the student to:
(cont)
• Explain the purpose of each of the four control
words of the 8259 and demonstrate how they
are programmed.
• Examine the interrupts in x86 PCs.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
• An interrupt is an external event that informs the
CPU that a device needs its service.
– In 8088/86 there are a total of 256 interrupts.
• INT 00, INT 01, ..., INT FF (sometimes called TYPEs).
• When an interrupt is executed the processor:
– Saves the flag register (FR), instruction pointer (IP),
and code segment register (CS) on the stack,.
– Goes to a fixed memory location.
• In x86, always four times the value of the interrupt number.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
interrupt service routine (ISR)
When an interrupt is invoked it is
asked to run a program to perform
a certain service.
There must be a program
associated with every interrupt .
This program is commonly referred
to as an interrupt service routine
(ISR), and also called the interrupt
handler.
When an interrupt is invoked, the
CPU runs the interrupt service
routine.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
interrupt service routine (ISR)
– For every interrupt there
are allocated four bytes
of memory in the interrupt
vector table.
– Two bytes for the IP.
– Two for the CS of the ISR.
• These locations provide the
addresses of the interrupt
service routine for which the
interrupt was invoked.
– The lowest 1024 bytes of
memory space are set aside
for the interrupt vector table.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
interrupt service routine (ISR)
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
differences between INT and CALL
• What is the difference between…
– INT instruction - which saves the CS:IP of the following
instruction and jumps indirectly to the subroutine
associated with the interrupt.
– A CALL FAR instruction, which also saves CS:IP
and jumps to the desired subroutine (procedure)?
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
differences between INT and CALL
• A "CALL FAR " instruction…
– can jump to any location within the 1-megabyte address
range of the 8088/86 CPU.
• The "INT nn" goes to a fixed memory location in the interrupt
vector table to get the address of the interrupt service routine.
– is used in the program instructions, but an externally
activated hardware interrupt can come in any time,
requesting CPU attention.
– cannot be masked (disabled), but "INT nn" belonging to
externally activated hardware interrupts can be masked.
– auto-saves only CS:IP of the next instruction on the stack.
• "INT nn" saves FR (flag register) also.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
differences between INT and CALL
• "INT nn" is a 2-byte instruction where the first byte
is for the opcode & the second the interrupt number.
– A maximum of 256 (INT 00 INT FFH) interrupts.
• Some are used for software interrupts; some for hardware.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
categories of interrupts
• Three x86 pins are associated with hardware
interrupts...
– INTR (interrupt request)
– NMI (nonmaskable interrupt)
– INTA (interrupt acknowledge)
• INTR is a CPU input signal, which can be masked
(ignored) & unmasked through use CLI and STI.
• NMI, also an input signal into the CPU, cannot be
masked and unmasked using CLI & STI.
– For this reason, it is called a nonmaskable interrupt.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
hardware interrupts
• INTR and NMI are activated externally by putting
5V on the x86 microprocessor NMI & INTR pins.
– On activation of either interrupt, x86:
• Finishes the instruction it is executing.
• Pushes FR & CS:IP of the next instruction onto the stack.
• Jumps to a fixed location in the interrupt vector table and
fetches the CS:IP for the interrupt service routine (ISR)
associated with that interrupt.
• At the end of the ISR, IRET causes the CPU to get
(pop) back its original FR and CS:IP from the stack.
– Forcing the CPU to continue at the instruction
where it left off when the interrupt came in.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
hardware interrupts
• Intel has embedded "INT 02" in x86, only for NMI.
– Whenthe NMI pin is activated, the CPU location 00008
to get the address (CS:IP) of the ISR.
• Memory locations 00008, 00009, 0000A, and 0000B
contain the 4 bytes of CS:IP of the ISR belonging to NMI.
• There is no specific location in the vector table
assigned to INTR.
– Allowed to use any "INT nn" not previously assigned.
– The 8259 programmable interrupt controller (PIC) chip
can be connected to INTR to expand the number of
hardware interrupts to 64.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
software interrupts
• An ISR called as a result of
execution of an x86 instruction
such as "INT nn“ is referred to
as a software interrupt.
– As it was invoked from software,
not external hardware.
• DOS "INT 21H" function calls,
and video interrupts "INT 10H".
• Can be invoked in code like a
CALL or other x86 instruction
• Some of the interrupts are
associated with predefined
functions.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
software interrupts
INT 00 to INT 04 have
predefined functions.
INT 00 (divide error)
INT 01 (single step)
INT 03 (breakpoint)
INT 04 (signed number overflow)
Interrupts INT 05 to INTFF
can be used for either
software or hardware
interrupts.
Figure 14-1 Intel's List of Designated Interrupts for the 8088/86
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
interrupts and the flag register
• Two flag register bits are associated with interrupt:
– D9, or IF (interrupt enable flag)
– D8, or TF (trap or single step flag).
– OF (overflow flag) can be used by the interrupt.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
processing interrupts
• When 8088/86 processes any interrupt:
– 1. The flag register (FR) is pushed onto the stack &
SP is decremented by 2, as FR is a 2-byte register.
– 2. The IF (interrupt enable flag) & TF (trap flag) are
both cleared. (IF = 0 and TF = 0).
– 3. The current CS is pushed onto the stack and
SP is decremented by 2.
– 4. The current IP is pushed onto the stack and SP
is decremented by 2.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
processing interrupts
• When 8088/86 processes any interrupt:
– 5. The INT number (type) is multiplied by 4 to get the
physical address of the location within the vector table
to fetch the CS and IP of the interrupt service routine.
– 6. From the new CS:IP, the CPU starts to fetch and
execute instructions belonging to the ISR program.
– 7. The last instruction of the interrupt service routine must
be IRET, to get IP, CS, and FR back from the stack and
make the CPU run the code where it left off.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
software interrupts
INT 00 to INT 04 have
predefined functions.
INT 00 (divide error)
A conditional or exception interrupt.
Invoked by the processor when there
are conditions (exceptions) the CPU
is unable to handle.
INT 00 invokes by when there is an
attempt to divide a number by zero.
INT 00 is also invoked if the quotient
is too large to fit into the assigned
register when executing a DIV.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
software interrupts
INT 00 to INT 04 have
predefined functions.
INT 01 (single step)
Intel designated INT 01 specifically
for implementation of single-stepping
instructions for program tracing.
The trap flag (TF), D8 of the flag
register, must be set to 1.
After execution of each instruction,
8088/86 jumps to physical location
00004 to fetch CS:IP of the interrupt
service routine.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
hardware interrupts
INT 00 to INT 04 have
predefined functions.
INT 02 (nonmaskable interrupt)
All Intel x86 processors have a pin
designated NMI, an active-high input,
and has reserved INT 02 for NMI.
When the NMI pin is activated by a
high (5V) signal, the CPU jumps to
physical memory location 00008 to
fetch the CS:IP of the ISR routine
associated with NMI.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
software interrupts
INT 00 to INT 04 have
predefined functions.
INT 03 (breakpoint)
Intel has set aside INT 03 for the
implementation of breakpoints in
software engineering.
A breakpoint is used to examine CPU
and memory after the execution of a
group of instructions.
INT 3 is the fact is a 1-byte instruction.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458
14.1: 8088/86 INTERRUPTS
software interrupts
INT 00 to INT 04 have
predefined functions.
INT 04 (signed number overflow)
Invoked by signed number overflow,
& associated with the INTO (interrupt
on overflow) instruction.
If instruction INTO is placed after a
signed number arithmetic or logic
operation such as IMUL or ADD, the
CPU will activate INT 04 if OF = 1.
If OF = 0, INTO is is bypassed, acting
as a NOP (no operation) instruction.
The x86 PC
Assembly Language, Design, and Interfacing
By Muhammad Ali Mazidi, Janice Gillespie Mazidi and Danny Causey
© 2010, 2003, 2000, 1998 Pearson Higher Education, Inc.
Pearson Prentice Hall - Upper Saddle River, NJ 07458