Transcript Chapter 2

Chapter 2
ARM Assembly Language
Programming and Architecture by
Mazidi et al
Ch.2 ARM Architecture and
Assembly Language
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GPRs –general purpose registers
Simple Instructions
Memory Map and Memory Access
Status register’s flag bits
Assembly language directives
Machine Language
Assembly
Step-by-step execution and the program counter
Addressing Modes
RISC architecure
Keil IDE
2.1 General Purpose Registers in
the ARM
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Registers store information temporarily.
All ARM registers are 32 bit wide.
1 word is usually called 32 bits (D31—D0)
1 half-word is 16 bits.
So byte, half-word and word data types
are supported.
• 13 GPRs—R0-R12.
Registers (cont.)
• Other microcontrollers have
accumulators—each of the ARM GPO
registers are similar.
• Special Purpose Registers
– R13—Stack Pointer
– R14—Link Register
– R15—Program Counter
ARM Instruction Format
• Example Format
– Instruction
destination, source1, source2
• Source2—can be a register, immediate
(constant) value, or memory.
MOV Instruction
• MOV Instruction
– Copies data into register or from register to
register
– Format—MOV RN,Op2 ; Op2 is loaded into
Rn
– Op2 can be immediate (constant) number
#K which is an 8-bit value.
– Op2 can also be a register.
– Example: MOV R1, #ox87 (R1 = ox87).
ARM Instructions (cont.)
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Note that the destination is first.
Note—”;” will denote comments.
Note--# is placed in front of immediate values.
Note—ox denotes a hex value.
Note—decimal values have “nothing” in front of
them (ex: MOV R1,#50) here 50 is decimal.
• The numbers are right justified and 0’s fill the
rest of the register.
• Immediate values cannot be larger than oxFF or
255 decimal.
ADD instruction
• ADD
Rd, Rn, Op2 ;
– Add Rn to Op2 and store the result in Rd.
– Op2 can be immediate or a register.
SUB Instruction
• SUB is like ADD.
• SUB
Rd, Rn, Op2
Unified Assembler
• Unified Assembler no longer recommends
the format discussed.
• If Rd and Rn are the same, then Rn are
can be omitted.
Some Other ALU Instructions
• ADC --ADD Rn to Op2 with Carry and place the result in
Rd.
• AND—AND Rn with OP2 and place the result in Rd.
• BIC—AND Rn with NOT of OP2 and place the result in
RD.
• CMP—Compare Rn with Op2 and set the status bits of
CPSR
• CMN—Compare Rn with negative of Op2 and set the
status bits
• EOR Exclusive OR RN with OP2 and place the result in
RD
• MVN– place Not of OP2 in Rd
Some Other ALU Instructions
• ORR– OR Rn with OP2 and place the
result in RD
• RSB –Subtract RN from OP2 and place
the result in Rd
• RSC—Subtract Rn from OP2 with darry
and place the result in Rd
• SBC—Subtract Op2 from Rn with carry
and place the result in Rd
2.2 The ARM Memory Map
• SFRs—special function registers
– R13 –stack pointer
– R14—link register ; holds the return address
when a subroutine is called.
– R15—Program Counter—accesses the next
instruction to execute.
– CPSR (current program status register)
Memory Map (cont.)
• Each location is 1 byte.
• Address Range
– Ox00000000 through oxFFFFFFFF
– This is 4G bytes of memory.
– Currently, not all of the 4G is on-chip.
Five Sections of ARM Memory
• On-chip peripheral and I/O (GPIO) and
special function registers of peripherals
(timers, serial communication and ADC.
• Memory-Mapped I/O.
• Address and function are fixed by the chip
vendor.
• The number of locations used for GPIO
registers can vary even with the same
vendor.
Memory (cont.)
• Section 2 of memory— On-chip data
SRAM.
• Data Storage (a few kilobytes to several hundred
kilobytes.
• Data variables, sscratch pad, and stack.
• Will vary from chip to chip.
Memory (cont.)
• 3. On-chip EEPROM
– 1K bytes to several thousand bytes
– Will vary from chip to chip.
• 4. On-chip Flash ROM
– A few kilobytes to several hundred kilobytes.
– Used for program code.
– Amount and location will vary from chip to chip.
• 5. Off-chip DRAM
– A few megabytes to several hundred megabytes.
EXAMPLE of MEMORY Allocation
• Special Function Registers (SFR)
– OxFFFF FFFF(4G) to OxFFFC 0000
• SRAM
– Ox4000 7FFF to Ox4000 0000 (1G)
• EEPROM
– Ox0010 1000 to Ox0010 0000
• FLASH
– Ox0007 FFFF to Ox0000 0000