Transcript esca.korea.ac.kr

ARM Instructions I
Prof. Taeweon Suh
Computer Science Education
Korea University
Data Processing Instructions
•
•
•
•
Arithmetic instructions
Logical instructions
Comparison instructions
Move instructions
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Execution Unit in ARM
Rn
(1st
Rm
source)
No pre-processing
Barrel Shifter
 Data processing instructions take 2 source
operands:
 One is always a register.
 The other is called a shifter operand (either
immediate or a register). If the second
operand is a register, it can have a shift
applied to it.
Pre-processing
N (=shifter_operand)
(2nd source)
ALU
Rd
 Source: ARM Architecture Reference Manual
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Arithmetic Instructions
Rn
Rm
Barrel
Shifter
N
ALU
Syntax: <instruction>{cond}{S} Rd, Rn, N
ADC
add two 32-bit values with carry
Rd = Rn + N + carry
ADD
add two 32-bit values
Rd = Rn + N
RSB
reverse subtract of two 32-bit values
Rd = N - Rn
RSC
reverse subtract of two 32-bit values
with carry
Rd = N – Rn - !C
SBC
subtract two 32-bit values with carry
Rd = Rn - N - !C
SUB
subtract two 32-bit values
Rd = Rn - N
Rd
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ARM Arithmetic Instructions
• ARM Arithmetic instructions include add, adc,
sub, sbc and some more
 Check out the Architecture Reference Manual for the
list of all arithmetic instructions
High-level code
ARM assembly code
compile
# R0 = a, R1 = b, R2 = c
add R0, R1, R2
a = b + c
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Arithmetic Instructions – ADD
• ADD adds two operands, placing the result in Rd
 Use S suffix to update conditional field
 The addition may be performed on signed or unsigned numbers
ADD R0, R1, R2 ; R0 = R1 + R2
ADD R0, R1, #256 ; R0 = R1 + 256
ADDS R0, R2, R3,LSL#1 ; R0 = R2 + (R3 << 1) and update flags
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add
add
1110
0
r1, r2, r3 # r1 <= r2 + r3
0
0001
0010
0 0 0 0 0 0 0 0
0011
ARM architect defines the opcode
binary
hexadecimal
1110
0000
1000
0010 0001
0000
0000
0011
0xe082 1003
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Immediate
• 8-bit immediate field in ARM instructions limits values to
the range of (0 ~ 255 (28–1))
 They are called immediates because they are
immediately available from the instructions
• They do not require a register or memory access
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add
add
1110
1
r4, r5, #255 # r4 <= r5 + 255
0
0100
0101
0000
1 1 1 1
1 1 11
ARM architect defines the opcode
binary
hexadecimal
1110
0010
1000
0101 0100
0000
1111
1111
0xe285 40ff
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Rm with Barrel Shifter
Encoded here
add r0, r1, r2, LSL #1
add r0, r1, r2, LSL r3
Shift Operation (for Rm)
Syntax
Immediate
Register
Logical shift left by immediate
Logical shift left by register
Logical shift right by immediate
Logical shift right by register
#immediate
Rm
Rm, LSL #shift_imm
Rm, LSL Rs
Rm, LSR #shift_imm
Rm, LSR Rs
Arithmetic shift right by
immediate
Rm, ASR #shift_imm
Arithmetic shift right by register
Rotate right by immediate
Rotate right by register
Rotate right with extend
Rm, ASR Rs
Rm, ROR #shift_imm
Rm, ROR Rs
Rm, RRX
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LSL: Logical Shift Left
LSR: Logical Shift Right
ASR: Arithmetic Shift Right
ROR: Rotate Right
RRX: Rotate Right with Extend
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Arithmetic Instructions – SUB
•
SUB subtracts operand 2 from operand 1, placing the result in Rd
 Use S suffix to update conditional field
 The subtraction may be performed on signed or unsigned numbers
SUB R0, R1, R2 ; R0 = R1 - R2
SUB R0, R1, #256 ; R0 = R1 - 256
SUBS R0, R2, R3,LSL#1 ; R0 = R2 - (R3 << 1) and update flags
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sub
sub
r4, r5, #255 # r4 <= r5 - 255
ARM architect defines the opcode
1110
1
0
0101
0100
0000
1 1 1 1
1 1 11
ARM architect defines the opcode
binary
hexadecimal
1110
0010
0100
0101 0100
0000
1111
1111
0xe245 40ff
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Examples
Before:
Before:
r0 = 0x0000_0000
r1 = 0x0000_0002
r2 = 0x0000_0001
r0 = 0x0000_0000
r1 = 0x0000_0005
SUB r0, r1, r2
ADD r0, r1, r1, LSL#1
After:
After:
r0 = 0x0000_0001
r1 = 0x0000_0002
r2 = 0x0000_0001
r0 = 0x0000_000F
r1 = 0x0000_0005
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Examples
Before:
cpsr = nzcv
r1 = 0x0000_0001
SUBS r1, r1, #1
After:
cpsr = nZCv
r1 = 0x0000_0000
• Why is the C flag set (C = 1)?
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Logical Instructions
Rn
Rm
Barrel
Shifter
N
ALU
Syntax: <instruction>{cond}{S} Rd, Rn, N
AND
logical bitwise AND of two 32-bit values
Rd = Rn & N
ORR
logical bitwise OR of two 32-bit values
Rd = Rn | N
EOR
logical exclusive OR of two 32-bit values
Rd = Rn ^ N
BIC
logical bit clear
Rd = Rn & ~N
Rd
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ARM Logical Instructions
• ARM logical instructions include and, orr, eor, bic
• Logical instructions operate bit-by-bit on 2 source
operands and write the result to the destination register
High-level code
ARM assembly code
compile
# R0 = a, R1 = b, R2 = c
and R0, R1, R2
a = b & c ;
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Logical Instructions – AND
•
AND performs a logical AND between the two operands, placing the
result in Rd
 It is useful for masking the bits
AND
R0, R0, #3 ; Keep bits zero and one of R0 and discard the rest
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Logical Instructions – EOR
•
EOR performs a logical Exclusive OR between the two operands,
placing the result in the destination register
 It is useful for inverting certain bits
EOR
R0, R0, #3 ; Invert bits zero and one of R0
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Examples
Before:
r0 = 0x0000_0000
r1 = 0x0204_0608
r2 = 0x1030_5070
Before:
r1 = 0b1111
r2 = 0b0101
BIC r0, r1, r2
ORR r0, r1, r2
After:
r0 = 0x1234_5678
After:
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r0 = 0b1010
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AND, OR, and EOR Usages
• and, or, nor
 and is useful for masking bits
• Example: mask all but the least significant byte of a value:
0xF234012F AND 0x000000FF = 0x0000002F
 or is useful for combining bit fields
• Example: combine 0xF2340000 with 0x000012BC:
0xF2340000 OR 0x000012BC = 0xF23412BC

eor is useful for inverting certain bits:
• Example: A EOR 3
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Comparison Instructions
• The comparison instructions update the cpsr flags
according to the result, but do not affect other
registers
Rn
Rm
Barrel
Shifter
• After the bits have been set, the information can
be used to change program flow by using
conditional execution
N
ALU
Rd
Syntax: <instruction>{cond}{S} Rn, N
CMN
compare negated
Flags set as a result of Rn + N
CMP
Compare
Flags set as a result of Rn – N
TEQ
test for equality of two 32bit values
Flags set as a result of Rn ^ N
TST
test bits of a 32-bit value
Flags set as a result of Rn & N
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Comparison Instructions – CMP
• CMP compares two values by subtracting the second
operand from the first operand
 Note that there is no destination register
 It only update cpsr flags based on the execution result
CMP R0, R1;
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Move Instructions
Rn
Rm
Barrel
Shifter
N
ALU
Syntax: <instruction>{cond}{S} Rd, N
MOV
Move a 32-bit value into a register
MVN
Move the NOT of the 32-bit value into a register Rd = ~ N
Rd = N
Rd
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Move Instructions – MOV
•
MOV loads a value into the destination register (Rd) from another
register, a shifted register, or an immediate value
 Useful to setting initial values and transferring data between
registers
 It updates the carry flag (C), negative flag (N), and zero flag (Z) if S bit is set
• C is set from the result of the barrel shifter
MOV R0, R0; move R0 to R0, Thus, no effect
MOV R0, R0, LSL#3 ; R0 = R0 * 8
MOV PC, R14; (R14: link register) Used to return to caller
MOVS PC, R14; PC <- R14 (lr), CPSR <- SPSR
; Used to return from interrupt or exception
* SBZ: should be zeros
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MOV Example
Before:
cpsr = nzcv
r0 = 0x0000_0000
r1 = 0x8000_0004
MOVS r0, r1, LSL #1
After:
cpsr = nzCv
r0 = 0x0000_0008
r1 = 0x8000_0004
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Branch Instructions
• A branch instruction changes the flow of execution or is
used to call a function
 This type of instructions allows programs to have subroutines,
if-then-else structures, and loops
Syntax: B{cond} label
BL{cond} label
B
branch
pc = label
BL
branch with link
pc = label
lr = address of the next instruction after the BL
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B, BL
• B (branch) and BL (branch with link) are used for conditional or
unconditional branch


BL is used for the subroutine (procedure, function) call
To return from a subroutine, use
• MOV PC, R14; (R14: link register) Used to return to caller
•
Branch target address




Sign-extend the 24-bit signed immediate (2’s complement) to 30-bits
Left-shift the result by 2 bits
Add it to the current PC (actually, PC+8)
Thus, the branch target could be ±32MB away from the current instruction
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Examples
B forward
ADD r1, r2, #4
ADD r0, r6, #2
ADD r3, r7, #4
forward:
SUB r1, r2, #4
backward:
ADD r1, r2, #4
SUB r1, r2, #4
ADD r4, r6, r7
B backward
BL my_subroutine
CMP r1, #5
MOVEQ r1, #0
…..
My_subroutine:
< subroutine code >
MOV pc, lr // return from subroutine
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Memory Access Instructions
• Load-Store (memory access) instructions transfer
data between memory and CPU registers
 Single-register transfer
 Multiple-register transfer
 Swap instruction
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Single-Register Transfer
LDR
Load a word into a register
Rd ← mem32[address]
STR
Store a word from a register to memory
Rd → mem32[address]
LDRB
Load a byte into a register
Rd ← mem8[address]
STRB
Store a byte from a register to memory
Rd → mem8[address]
LDRH
Load a half-word into a register
Rd ← mem16[address]
STRH
Store a half-word into a register
Rd → mem16[address]
LDRSB
Load a signed byte into a register
LDRSH
Load a signed half-word into a register
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Rd ← SignExtend (
mem8[address])
Rd ← SignExtend (
mem16[address])
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LDR (Load Register)
• LDR loads a word from a memory location to a register
 The memory location is specified in a very flexible manner with
addressing mode
// Assume R1 = 0x0000_2000
LDR R0, [R1] // R0 ← [R1]
LDR R0, [R1, #16] // R0 ← [R1+16]; 0x0000_2010
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STR (Store Register)
• STR stores a word from a register to a memory location
 The memory location is specified in a very flexible manner with a
addressing mode
// Assume R1 = 0x0000_2000
STR R0, [R1] // [R1] <- R0
STR R0, [R1, #16] // [R1+16] <- R0
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CPU Execution Example (ARM)
Register File
32 bits
ARM CPU
PC (r15)
0x0000
0x0004
0x0008
r0
r1
Address Bus
0x00110011
r2
0x0014
0x0018
r3
0x00220022
…
+
Memory
0x00220022
0x00110011
0x0018
0x0014
add
ldr
ldr
ldr
0x0008
0x0004
0x0000
R3
0x00330033
Data Bus
r13
r14
r2, r2, r3
r3, [r13, 8]
r2,
r2, [r13,
[r13, 4]
4]
Assume that r13 contains 0x0010
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Load-Store Addressing Mode
Indexing Method Data
Base Address register
updated?
Example
Preindex with
writeback
Mem[base + offset]
Yes (Base + offset)
LDR r0, [r1, #4]!
Preindex
Mem[base + offset]
No
LDR r0, [r1, #4]
Postindex
Mem[base]
Yes (Base + offset)
LDR r0, [r1], #4
! Indicates that the instruction writes the calculated address back to the base address register
LDR r0, [r1, #4]!
Before:
r0 = 0x0000_0000
r1 = 0x0009_0000
Mem32[0x0009_0000] = 0x01010101
Mem32[0x0009_0004] = 0x02020202
LDR r0, [r1, #4]
LDR r0, [r1], #4
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After: r0 ← mem[0x0009_0004]
r0 = 0x0202_0202
r1 = 0x0009_0004
After: r0 ← mem[0x0009_0004]
r0 = 0x0202_0202
r1 = 0x0009_0000
After: r0 ← mem[0x0009_0000]
r0 = 0x0101_0101
r1 = 0x0009_0004
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(Assembly) Language
• There is no golden way to learn language
• You got to use and practice to get used to it
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Backup Slides
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