Transcript AssemblyLanguage02

II
Prof. Muhammad Saeed
1/27/2015
Computer Architecture & Assembly
Language
2
Fundamentals (recap)
 Number System
 Binary
 Octal
 Hexa
 Conversion into one another
 Binary Operations
Addition, Subtraction and Multiplication
AND, OR, XOR
COMPLEMENT, TWO’s COMPLEMENT
Set and Reset Bits
1/27/2015
Computer Architecture & Assembly
Language
3
Interrupts
An interrupt is a signal to the processor emitted by
hardware or software indicating an event that needs
immediate attention. An interrupt alerts the
to a high-priority condition requiring the interruption
of the current code the processor is executing. The
processor responds by suspending its current
activities, saving its state, and executing
a function called an interrupt handler (or an interrupt
service routine, ISR) to deal with the event. This
interruption is temporary, and, after the interrupt
handler finishes, the processor resumes normal
activities.
1/27/2015
Computer Architecture & Assembly
Language
4
Interrupt
1/27/2015
Computer Architecture & Assembly
Language
5
Interrupts
TYPES
Hardware interrupts are used by internal or external devices to
communicate that they require attention from the operating system.
Pressing a key on the keyboard or moving the mouse triggers hardware
interrupts that cause the processor to read the keystroke or mouse
position. Unlike the software type hardware interrupts
are asynchronous and can occur in the middle of instruction execution.
A software interrupt is caused either by an exceptional condition
in the processor itself, or a special instruction in the instruction
set which causes an interrupt when it is executed. The former is often
called a trap or exception and is used for errors or events occurring
during program. For example, if the processor's arithmetic logic unit is
commanded to divide a number by zero, this impossible demand will
cause a divide-by-zero exception. Computers often use software
interrupt instructions to communicate with the device drivers.
1/27/2015
Computer Architecture & Assembly
Language
6
Interrupts
 Interrupt Service Routine (ISR) or Interrupt handler:
Code used for handling a specific interrupt.
 Interrupt priority:
In systems with more than one interrupt inputs, some interrupts
have a higher priority than other. They are serviced first if multiple
interrupts are triggered simultaneously.
 Interrupt vector:
Code loaded on the bus by the interrupting device that contains
the Address (segment and offset) of specific interrupt service
routine.
 Interrupt Masking:
Ignoring (disabling) an interrupt
 Non-Maskable Interrupt (NMI):
Interrupt that cannot be ignored (power-down)
1/27/2015
Computer Architecture & Assembly
Language
7
The Intel x86 Vector Interrupts
8088/8086 processor as well as 80386/80486/
Pentium etc. processors operating in Real Mode
(16-bit operation)
 The processor uses the interrupt vector to determine the address of the
ISR of the interrupting device.
 The interrupt vector is a pointer to the Interrupt Vector Table.
 The Interrupt Vector Table occupies the address range from
00000H to 003FFH (the first 1024 bytes in the memory map).
 Each entry in the Interrupt Vector Table is 4 bytes long:
 The first two represent the offset address and the last two the
segment address of the ISR.
 The first 5 vectors are reserved by Intel to be used by the
processor.
 The vectors 5 to 255 are free to be used by the user.
1/27/2015
Computer Architecture & Assembly
Language
8
The Intel x86 Vector Interrupts
IP
Type-0
CS
Type-1
Interrupt Vector Table
•••••
8088/8086 processor as well as
80386/80486/ Pentium etc. processors
operating in Real Mode (16-bit
operation)
Type-255
003FFH
1/27/2015
Computer Architecture & Assembly
Language
9
Interrupt Vector Table – Real Mode
 Using the Interrupt Vector Table shown below, determine the address of
the ISR of a device with interrupt vector 42H.
 Answer: Address in table = 4 X 42H = 108H
 Offset Low = [108] = 2A,
Offset High = [109] = 33
 Segment Low = [10A] = 3C,
Segment High = [10B] = 4A
 Address = 4A3C:332A = 4A3C0 + 332A = 4D6EAH
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
00000
3C
22
10
38
6F
13
2C
2A
33
22
21
67
EE
F1
32
25
00010
.........
00100
11
...
4A
3C
...
33
32
...
3C
88
...
4A
90
...
AA
16
...
1A
44
...
1B
32
...
A2
14
...
2A
30
...
33
42
...
3C
58
...
4A
30
...
AA
36
...
1A
34
...
3E
66
...
77
00110
.........
00250
C1
...
00
58
...
10
4E
...
10
C1
...
20
4F
...
3F
11
...
26
66
...
33
F4
...
3C
C5
...
20
58
...
26
4E
...
20
20
...
C1
4F
...
3F
11
...
10
F0
...
28
F4
...
32
00260
.........
003E0
20
...
3A
4E
...
10
00
...
45
10
...
2F
50
...
4E
88
...
33
22
...
6F
38
...
90
10
...
3A
5A
...
44
38
...
37
10
...
43
4C
...
3A
55
...
54
14
...
54
54
...
7F
003F0
22
3C
80
01
3C
4F
4E
88
22
3C
50
21
49
3F
F4
65
1/27/2015
Computer Architecture & Assembly
Language
10
The Intel x86 Vector Interrupts
80386/80486/Pentium processors operating in
Protected Mode (32-bit operation)
 The interrupt vector is a pointer to the Interrupt Descriptor
Table.
 The Interrupt Descriptor Table can be located anywhere in
the memory.
 Its starting address is pointed by the Interrupt
Descriptor Table Register (IDTR).
 Each entry in the Interrupt Vector Table is 8 bytes long:
 Four bytes represent the 32-bit offset address, two
the segment selector and the rest information such as
the privilege level.
 The first 32 vectors are reserved by Intel to be used by the
processor.
 The vectors 33 to 255 are free to be used by the
user.
1/27/2015
Computer Architecture & Assembly
Language
11
The Intel x86 Vector Interrupts
The protected mode
interrupt descriptor
1/27/2015
7
Offset (A31 - A16)
6
5 PF
01110
4
00H
3
Segment Selector
2
1
Offset (A15 - A0)
0
Computer Architecture & Assembly
Language
12
Access Levels
1/27/2015
Computer Architecture & Assembly
Language
13
Language Fundamentals
† Identifiers
An identifier is a programmer-chosen name. It might
identify a variable, a constant, a procedure, or a code
label. There are a few rules on how they can be formed:
• They may contain between 1 and 247 characters.
• They are not case sensitive.
• The first character must be a letter (A..Z, a..z),
underscore (_), @ , ?, or $. Subsequent
characters may also be digits.
• An identifier cannot be the same as an assembler
reserved word.
1/27/2015
Computer Architecture & Assembly
Language
14
Language Fundamentals
† Data Types
1/27/2015
Computer Architecture & Assembly
Language
15
Language Fundamentals
† 8088 Data Type Directives
1/27/2015
Computer Architecture & Assembly
Language
16
Language Fundamentals
† Label
A label is an identifier that acts as a place marker for
instructions and data. A label placed just before an
instruction implies the instruction’s address. Similarly, a label
placed just before a variable implies the variable’s address.
There are two types of labels: Data labels and Code labels.
A data label identifies the location of a variable, providing a
convenient way to reference the variable in code.
Data Label: a1
BYTE 86 ( a1 is Data Label)
Code Label: again: mov eax, 100h (again is Code Label)
1/27/2015
Computer Architecture & Assembly
Language
17
Language Fundamentals
† Directive And Instruction
Directive instructs assembler how to assemble a
program, in other word it is an instruction for the
assembler whereas assembly Instruction is for the
processor and it is converted to machine code.
Directive is not converted to machine code.
Directives do not execute at runtime, but they let
you define variables, macros, and procedures. They
can assign names to memory segments and perform
many other housekeeping tasks related to the
assembler.
Directives: INCLUDE (INCLUDE windows.inc, INCLUDELIB
windows.lib), .MODEL,.DATA, .CODE, WORD, etc.
1/27/2015
Computer Architecture & Assembly
Language
18
Language Fundamentals
† Defining Data
a1
a2
a3
a4
a5
a6
a7
a8
quote
1/27/2015
BYTE
BYTE
BYTE
BYTE
BYTE
SBYTE
SBYTE
SBYTE
BYTE
BYTE
BYTE
86
‘K’
“Welcome to Dept. of Comp. Sc. & IT”,0
255
?
-128
127
0, 20, 50, -25, 100
“There are no tales”
“ finer than those”, 0dh, 0ah
“created by life itself”,0dh, oah,0
Computer Architecture & Assembly
Language
19
Language Fundamentals
† Defining Data (ARRAYS)
Array1
Array2
Array3
BYTE 10
WORD 20
BYTE 10
DUP(?)
DUP(0)
DUP(‘COMPUTER’)
† Segments
 Stack
 Data
 Code
(.stack 1024)
(.data)
(.code)
† Comments
single line comment starts with “;” and the block comment
is used as, COMMENT ! ……..
………………….. ! (! Character can be replaced by & etc.)
1/27/2015
Computer Architecture & Assembly
Language
20
Fundamentals
† Little-Endians
x86 processors store and retrieve data from
memory using little-endian order(low to high). The least
significant byte is stored at the first memory address
allocated for the data. The remaining bytes are stored in
the next consecutive memory positions. The doubleword
12345678h is stored as given in the opposite figure.
† Big-Endians
Some other computer systems use big-endian order
(high to low). Figure on the right shows the same
example of 12345678h stored in big-endian order
1/27/2015
Computer Architecture & Assembly
Language
21
Memory Addressing
1/27/2015
Computer Architecture & Assembly
Language
22
Language Fundamentals
1st Program
.586
.MODEL flat, stdcall
option casemap :none
includeD:\msaeed\academic\assemblylanguage\masm32\include\windows.inc
includeD:\msaeed\academic\assemblylanguage\masm32\include\kernel32.inc
includeD:\msaeed\academic\assemblylanguage\masm32\include\user32.inc
includelibD:\msaeed\academic\assemblylanguage\masm32\lib\kernel32.lib
includelibD:\msaeed\academic\assemblylanguage\masm32\lib\user32.lib
.DATA
WindowTitle
Message
BYTE
BYTE
“Greetings",0
“Hello, World",0
.CODE
main:
invoke MessageBox, NULL, ADDR Message, ADDR WindowTitle, MB_OK
invoke ExitProcess, eax
end main
1/27/2015
Computer Architecture & Assembly
Language
23
Language Fundamentals
† MOV
MOV
MOV
MOV
MOV
MOV
reg, reg
mem, reg
reg, mem
mem, imm
reg, imm
† MOVZX
MOVZX reg32, reg/mem8
MOVZX reg32, reg/mem16
MOVZX reg16, reg/mem8
† MOVSX
MOVSX reg32, reg/mem8
MOVSX reg32, reg/mem16
MOVSX reg16, reg/mem8
1/27/2015
Computer Architecture & Assembly
Language
24
Language Fundamentals
† XCHG
XCHG reg, reg
XCHG reg, mem
XCHG mem, reg
† INC, DEC
INC reg/mem
DEC reg/mem
The Overflow, Sign, Zero, Auxiliary Carry, and Parity
flags are changed according to the value of the
destination operand.
† ADD, SUB
ADD dest, source The Carry, Zero, Sign, Overflow, Auxiliary Carry, and
SUB dest, source Parity flags are changed according to the value that is
placed in the destination operand.
† NEG
NEG reg
NEG mem
1/27/2015
The Carry, Zero, Sign, Overflow, Auxiliary Carry, and
Parity flags are changed according to the value that is
placed in the destination operand.
Computer Architecture & Assembly
Language
25
Language Fundamentals
Data-Related Operators and Directives
 The OFFSET operator returns the distance of a variable from the
beginning of its enclosing segment.
 The PTR operator lets you override an operand’s default size.
 The TYPE operator returns the size (in bytes) of an operand or of
each element in an array.
 The LENGTHOF operator returns the number of elements in an
array.
 The SIZEOF operator returns the number of bytes used by an array
initializer.
 The LABEL directive provides a way to redefine the same variable
with different size attributes.
Language Fundamentals
Language Fundamentals
END