Transcript Ch3

COM 249 – Computer Organization and
Assembly Language
Chapter 3
Arithmetic for Computers
Based on slides from D. Patterson and
www-inst.eecs.berkeley.edu/~cs152/
Modified by S. J. Fritz Spring 2009 (1)
Arithmetic
• Where we've been:
– Performance (seconds, cycles, instructions)
– Abstractions:
Instruction Set Architecture
Assembly Language and Machine Language
• What's up ahead:
– Implementing the Architecture operation
a
32
ALU
result
32
b
32
Modified by S. J. Fritz Spring 2009 (2)
• Operations on integers
– Addition and subtraction
– Multiplication and division
– Dealing with overflow
• Floating-point real numbers
– Representation and operations
Modified by S. J. Fritz Spring 2009 (3)
§3.1 Introduction
Arithmetic for Computers
Numbers
• Bits are just bits (no inherent meaning)
- conventions define relationship between bits and
numbers
• Binary numbers (base 2)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001...
decimal: 0...2n-1
• Of course it gets more complicated:
-numbers are finite (overflow)
-fractions and real numbers
-negative numbers
-no MIPS subi instruction; addi can add a negative
number
Modified by S. J. Fritz Spring 2009 (4)
Numbers
• How do we represent negative numbers?
-which bit patterns will represent which numbers?
• What is the largest number that can be
represented in a computer?
• How does hardware REALLY multiply or divide
numbers?
Modified by S. J. Fritz Spring 2009 (5)
Possible Representations
•
Sign Magnitude:
000 = +0
001 = +1
010 = +2
011 = +3
100 = -0
101 = -1
110 = -2
111 = -3
One's Complement
Two's Complement
000 = +0
001 = +1
010 = +2
011 = +3
100 = -3
101 = -2
110 = -1
111 = -0
111 = -1
• Issues: balance, number of zeros, ease of operations
• Which one is best? Why?
Modified by S. J. Fritz Spring 2009 (6)
000 = +0
001 = +1
010 = +2
011 = +3
100 = -4
101 = -3
110 = -2
MIPS
•
32 bit signed numbers:
0000 0000 0000 0000 0000 0000 0000 0000two = 0ten
0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten
0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten
...
0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten
0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten
1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten
1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten
...
1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten
1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten
1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten
Modified by S. J. Fritz Spring 2009 (7)
maxint
minint
Two's Complement Operations
• Negating a two's complement number: invert all bits and add 1
– remember: “negate” and “invert” are quite different!
– Example: 8 bit representation of 5
– Binary
0000 0101
– Invert
1111 1010
– Add 1
( 5 two)
+ 1
1111 1011
( -5 two)
• Interpreting a two’s complement number
• First bit is sign bit
• 1 x 2-7 + 1 x26 + 1x 25+ 1x24 + 1x 23 + 0x 22 + 1x21 + 1x 20
• -128
+ 64
+ 32
+ 16 + 8
+0
+2 +
1 = -5
• Adding a number and it’s twos complement equals zero!
Modified by S. J. Fritz Spring 2009 (8)
• Example: 7 + 6
• Overflow if result out of range
– Adding + and –operands, no overflow
– Adding two + operands
• Overflow if result sign is 1
– Adding two – operands
• Overflow if result sign is 0
Modified by S. J. Fritz Spring 2009 (9)
§3.2 Addition and Subtraction
Integer Addition
Integer Subtraction
• Add negation of second operand
• Example: 7 – 6 = 7 + (–6)
+7:
–6:
+1:
0000 0000 … 0000 0111
1111 1111 … 1111 1010
0000 0000 … 0000 0001
• Overflow if result out of range
– Subtracting two + or two – operands, no overflow
– Subtracting + from – operand
• Overflow if result sign is 0
– Subtracting – from + operand
• Overflow if result sign is 1
Modified by S. J. Fritz Spring 2009 (10)
Addition & Subtraction
• Just like in grade school (carry / borrow 1s)
0111
0111
+ 0110
- 0110
0110
- 0101
• Two's complement operations easy
– subtraction using addition of negative numbers
0111
+ 1010
– Overflow (result too large for finite computer word):
– e.g., adding two n-bit numbers does not always yield an n-bit
number
1111
+ 0001
note that overflow term is somewhat misleading,
10000
it does not mean a carry “overflowed”
Modified by S. J. Fritz Spring 2009 (11)
Arithmetic Practice
• Two’s Complement
http://scholar.hw.ac.uk/site/computing/topic18.asp?outline= (explained)
http://scholar.hw.ac.uk/site/computing/activity12.asp?outline (simulator)
• Data Representation and Number Systems
http://scholar.hw.ac.uk/site/computing/topic1.html
• Subtraction
http://scholar.hw.ac.uk/site/computing/activity14.html
• Logical Operations and Operators
http://scholar.hw.ac.uk/site/computing/topic35.html
Modified by S. J. Fritz Spring 2009 (12)
Overflow
• Overflow occurs when the result of an
operation on n bits > n bits
• Example: adding two 8 bit values
1001 1101
157
+1111 1011
+251
11001 1000
408
overflow!
Modified by S. J. Fritz Spring 2009 (13)
Detecting Overflow
• Overflow occurs when the result cannot be represented in
the available hardware
• No overflow when adding a positive and a negative number
• No overflow when signs are the same for subtraction
• Overflow occurs when the value affects the sign:
– overflow when adding two positives yields a negative
– or, adding two negatives gives a positive
– or, subtract a negative from a positive and get a negative
– or, subtract a positive from a negative and get a positive
• Consider the operations A + B, and A – B (See table p. 226)
– Can overflow occur if B is 0 ?
– Can overflow occur if A is 0 ?
Modified by S. J. Fritz Spring 2009 (14)
Effects of Overflow
• An exception (interrupt) occurs
– Control jumps to predefined address for exception
– Interrupted address is saved for possible resumption
– add, addi, sub cause exceptions on overflow but
– addu, addiu, subu DO NOT cause exceptions
• Details based on software system / language
– example: flight control vs. homework assignment
• Don't always want to detect overflow
— new MIPS instructions: addu, addiu, subu
note: addiu still sign-extends!
note: sltu, sltiu for unsigned comparisons
Modified by S. J. Fritz Spring 2009 (15)
Dealing with Overflow in MIPS
• Some languages (e.g., C) ignore overflow
– Use MIPS addu, addui, subu instructions
• Other languages (e.g., Ada, Fortran) require
raising an exception
– Use MIPS add, addi, sub instructions
– MIPS detects overflow with an exception or interrupt
– On overflow, invoke exception handler
• Address of instruction that overflowed is stored in a register
• Saves address in exception program counter (EPC) register
• Jumps to predefined exception handler address
• mfc0 (move from coprocessor reg) instruction can retrieve
EPC value, to return after corrective action
Modified by S. J. Fritz Spring 2009 (16)
Signed and Unsigned
• MIPS – two versions of set on less than comparison
– for signed integers
slt (set on less than) and slti (set on less than immediate)
– for unsigned integers
sltu(set on less than unsigned) and sltiu (set on less than immediate
unsigned)
slt $s1,$s2,$s3 means if ($s2 < $s3) $s1 = 1 //compare two’s complement
else $s1 =0
slti $s1,$s2, 100 means if ( $s2 < 100) $s1 = 1 //compare to constant
else $s1 =0
sltu $s1,$s2,$s3 means if ($s2 < $s3) $s1 = 1 //compares unsigned
else $s1 =0
sltiu $s1,$s2, 100 means if ($s2 < 100) $s1 =1 //compare to constant
else $s1 =0
Modified by S. J. Fritz Spring 2009 (17)
Shortcuts
• To negate two’s complement binary number
– Invert each bit and add one to result
– Based on based on observation that the sum of a
number and the representation of its inverse = -1
• To convert a number with n bits to a number
represented with more than n bits
– Take the most significant bit (sign bit) from the shorter
number, and replicate it to fill the new bits of the longer
number. ( Copy the original bits into the right portion of
the new word – called sign extension)
Modified by S. J. Fritz Spring 2009 (18)
Arithmetic for Multimedia
• Graphics systems originally used 8 bits for each of
the three colors (RGB), plus 8 bits for the location
of the pixel (picture element)
• Sound required 16 bits for audio samples.
• Microprocessors have special support so that bytes
and half-words take up less space, when stored in
memory
• Graphics and audio perform simultaneous
operations on vectors of data, using a partitioned
adder. These are called SIMD ( Single Instruction,
Multiple Data)
Modified by S. J. Fritz Spring 2009 (19)
Arithmetic for Multimedia
• Graphics and media processing operates on
vectors of 8-bit and 16-bit data
– Use 64-bit adder, with partitioned carry chain
• Operate on 8×8-bit, 4×16-bit, or 2×32-bit vectors
– SIMD (single-instruction, multiple-data)
• Saturating operations – when a calculation
overflows the result is set to the largest positive
number, or most negative number
– On overflow, result is largest representable value
• Instead of 2s-complement modulo arithmetic
• Like turning a volume knob
– E.g., clipping in audio, saturation in video
(See table page 228)
Modified by S. J. Fritz Spring 2009 (20)
• Start with long-multiplication approach
multiplicand
multiplier
product
1000
× 1001
1000
0000
0000
1000
1001000
Modified by S. J. Fritz Spring 2009 (21)
§3.3 Multiplication
Multiplication
Shift Registers
If we analyze long multiplication in terms of how we do it in
the decimal number system, we will see that it is a
combination of SHIFTS and ADDS.
Shift Registers
Example: 1910 x 510
Multiplicand
1 0 0 1 1 = 19
x
1 0 1 = x5
1 0 0 1 1
Multiplier
0 0 0 0 0 0
1 0 0 1 1 0 0
1 0 1 1 1 1 1 = 9510
Product
The multiplication is
achieved by adding
in the multiplicand
every time there is a
‘1’ in the multiplier
and adding in zero
every time there is a
‘0’ in the multiplier,
shifting up to next
digit each time.
Full Binary Multiplication
•Multiplying two n-bit numbers together may possibly
generate a 2n-bit result.
•So two registers are typically needed to hold the
result.
•Consider the multiplication of 7 by 5 on a 4-bit computer
Full Binary Multiplication
Add in
here
Shift in
here
0000
0111
xxxx
xxxx
0011
0011
0001
1000
0100
0100
0010
1xxx
1xxx
11xx
11xx
011x
011x
0011
0111
0101
= 7 multiplicand
= 5 multiplier
•Start at ALL zero’s...
•Bit 0 is a 1 => Add in the Multiplier
•Shift Across to the right.
•Bit 1 is a 0 => Add in 0000 (zero)
•Shift Across to the right
•Bit 2 is a 1 => Add in the Multiplier
•Shift Across to the right
•Bit 3 is a 0 => Add in 0000 (zero)
•Shift Across to the right. ANS=3510
Multiplication Hardware
Initially 0
Modified by S. J. Fritz Spring 2009 (26)
Optimized Multiplier
• Perform steps in parallel: add/shift
• One cycle per partial-product addition
– That’s ok, if frequency of multiplications is low
Modified by S. J. Fritz Spring 2009 (27)
Faster Multiplier
• Uses multiple adders
– Cost/performance tradeoff
• Can be pipelined
– Several multiplication performed in parallel
Modified by S. J. Fritz Spring 2009 (28)
MIPS Multiplication
• Two 32-bit registers for product
– HI: most-significant 32 bits
– LO: least-significant 32-bits
HI
LO
• Instructions
– mult rs, rt
/
multu rs, rt
• 64-bit product in HI/LO
– mfhi rd
/
mflo rd
• Move from HI/LO to rd
• Can test HI value to see if product overflows 32 bits
– mul rd, rs, rt
• Least-significant 32 bits of product –> rd
Modified by S. J. Fritz Spring 2009 (29)
quotient
dividend
• Check for 0 divisor
• Long division approach
– If divisor ≤ dividend bits
• 1 bit in quotient, subtract
1001
– Otherwise
1000 1001010
• 0 bit in quotient, bring down next
-1000
divisor
dividend bit
10
101 • Restoring division
1010
– Do the subtract, and if remainder
-1000
goes < 0, add divisor back
10 • Signed division
remainder
– Divide using absolute values
n-bit operands yield n-bit
– Adjust sign of quotient and
quotient and remainder
remainder as required
Modified by S. J. Fritz Spring 2009 (30)
§3.4 Division
Division
Division Hardware
Initially divisor
in left half
Initially dividend
Modified by S. J. Fritz Spring 2009 (31)
Optimized Divider
• One cycle per partial-remainder subtraction
• Looks a lot like a multiplier!
– Same hardware can be used for both
Modified by S. J. Fritz Spring 2009 (32)
Faster Division
• Can’t use parallel hardware as in multiplier
– Subtraction is conditional on sign of remainder
• Faster dividers (e.g. SRT division) generate
multiple quotient bits per step
– Still require multiple steps
Modified by S. J. Fritz Spring 2009 (33)
MIPS Division
• Use HI/LO registers for result
– HI: 32-bit remainder
– LO: 32-bit quotient
HI ( remainder)
LO (quotient)
• Instructions
– div rs, rt / divu rs, rt
– No overflow or divide-by-0 checking
• Software must perform checks if required
– Use mfhi, mflo to access result
Modified by S. J. Fritz Spring 2009 (34)
• Representation for non-integral numbers
– Including very small and very large numbers
• Like scientific notation
– –2.34 × 1056
– +0.002 × 10–4
– +987.02 × 109
normalized
not normalized
• In binary
– ±1.xxxxxxx2 × 2yyyy
• Types float and double in C
Modified by S. J. Fritz Spring 2009 (35)
§3.5 Floating Point
Floating Point
Floating Point Standard
• Defined by IEEE Std 754-1985
• Developed in response to divergence of
representations
– Portability issues for scientific code
• Now almost universally adopted
• Two representations
– Single precision (32-bit)
– Double precision (64-bit)
Modified by S. J. Fritz Spring 2009 (36)
IEEE Floating-Point Format
single: 8 bits
double: 11 bits
S Exponent
single: 23 bits
double: 52 bits
Fraction
x  (1)S  (1 Fraction)  2(Exponent Bias)
• S: sign bit (0  non-negative, 1  negative)
• Normalize significand: 1.0 ≤ |significand| < 2.0
– Always has a leading pre-binary-point 1 bit, so no need to represent
it explicitly (hidden bit)
– Significand is Fraction with the “1.” restored
• Exponent: excess representation: actual exponent + Bias
– Ensures exponent is unsigned
– Single: Bias = 127; Double: Bias = 1203
Modified by S. J. Fritz Spring 2009 (37)
Single-Precision Range
• Exponents 00000000 and 11111111 reserved
• Smallest value
– Exponent: 00000001
 actual exponent = 1 – 127 = –126
– Fraction: 000…00  significand = 1.0
– ±1.0 × 2–126 ≈ ±1.2 × 10–38
• Largest value
– exponent: 11111110
 actual exponent = 254 – 127 = +127
– Fraction: 111…11  significand ≈ 2.0
– ±2.0 × 2+127 ≈ ±3.4 × 10+38
Modified by S. J. Fritz Spring 2009 (38)
Double-Precision Range
• Exponents 0000…00 and 1111…11 reserved
• Smallest value
– Exponent: 00000000001
 actual exponent = 1 – 1023 = –1022
– Fraction: 000…00  significand = 1.0
– ±1.0 × 2–1022 ≈ ±2.2 × 10–308
• Largest value
– Exponent: 11111111110
 actual exponent = 2046 – 1023 = +1023
– Fraction: 111…11  significand ≈ 2.0
– ±2.0 × 2+1023 ≈ ±1.8 × 10+308
Modified by S. J. Fritz Spring 2009 (39)
Floating-Point Precision
• Relative precision
– all fraction bits are significant
– Single: approx 2–23
• Equivalent to 23 × log102 ≈ 23 × 0.3 ≈ 6 decimal
digits of precision
– Double: approx 2–52
• Equivalent to 52 × log102 ≈ 52 × 0.3 ≈ 16
decimal digits of precision
Modified by S. J. Fritz Spring 2009 (40)
Floating-Point Example
• Represent –0.75
– –0.75 = (–1)1 × 1.12 × 2–1
–S=1
– Fraction = 1000…002
– Exponent = –1 + Bias
• Single: –1 + 127 = 126 = 011111102
• Double: –1 + 1023 = 1022 = 011111111102
• Single: 1011111101000…00
• Double: 1011111111101000…00
Modified by S. J. Fritz Spring 2009 (41)
Floating-Point Example
• What number is represented by the
single-precision float
11000000101000…00
–S=1
– Fraction = 01000…002
– Fxponent = 100000012 = 129
• x = (–1)1 × (1 + 012) × 2(129 – 127)
= (–1) × 1.25 × 22
= –5.0
Modified by S. J. Fritz Spring 2009 (42)
Floating-Point Addition
• Consider a 4-digit decimal example
– 9.999 × 101 + 1.610 × 10–1
• 1. Align decimal points
– Shift number with smaller exponent
– 9.999 × 101 + 0.016 × 101
• 2. Add significands
– 9.999 × 101 + 0.016 × 101 = 10.015 × 101
• 3. Normalize result & check for over/underflow
– 1.0015 × 102
• 4. Round and renormalize if necessary
– 1.002 × 102
Modified by S. J. Fritz Spring 2009 (45)
Floating-Point Addition
• Now consider a 4-digit binary example
– 1.0002 × 2–1 + –1.1102 × 2–2 (0.5 + –0.4375)
• 1. Align binary points
– Shift number with smaller exponent
– 1.0002 × 2–1 + –0.1112 × 2–1
• 2. Add significands
– 1.0002 × 2–1 + –0.1112 × 2–1 = 0.0012 × 2–1
• 3. Normalize result & check for over/underflow
– 1.0002 × 2–4, with no over/underflow
• 4. Round and renormalize if necessary
– 1.0002 × 2–4 (no change) = 0.0625
Modified by S. J. Fritz Spring 2009 (46)
FP Adder Hardware
• Much more complex than integer adder
• Doing it in one clock cycle would take
too long
– Much longer than integer operations
– Slower clock would penalize all instructions
• FP adder usually takes several cycles
– Can be pipelined
Modified by S. J. Fritz Spring 2009 (47)
FP Adder Hardware
Step 1
Step 2
Step 3
Step 4
Modified by S. J. Fritz Spring 2009 (48)
FP Arithmetic Hardware
• FP multiplier is of similar complexity to FP
adder
– But uses a multiplier for significands instead of an
adder
• FP arithmetic hardware usually does
– Addition, subtraction, multiplication, division,
reciprocal, square-root
– FP  integer conversion
• Operations usually takes several cycles
– Can be pipelined
Modified by S. J. Fritz Spring 2009 (51)
FP Instructions in MIPS
• FP hardware is coprocessor 1
– Adjunct processor that extends the ISA
• Separate FP registers
– 32 single-precision: $f0, $f1, … $f31
– Paired for double-precision: $f0/$f1, $f2/$f3, …
• Release 2 of MIPs ISA supports 32 × 64-bit FP reg’s
• FP instructions operate only on FP registers
– Programs generally don’t do integer ops on FP data, or vice
versa
– More registers with minimal code-size impact
• FP load and store instructions
– lwc1, ldc1, swc1, sdc1
• e.g., ldc1 $f8, 32($sp)
Modified by S. J. Fritz Spring 2009 (52)
FP Instructions in MIPS
• Single-precision arithmetic
– add.s, sub.s, mul.s, div.s
• e.g., add.s $f0, $f1, $f6
• Double-precision arithmetic
– add.d, sub.d, mul.d, div.d
• e.g., mul.d $f4, $f4, $f6
• Single- and double-precision comparison
– c.xx.s, c.xx.d (xx is eq, lt, le, …)
– Sets or clears FP condition-code bit
• e.g. c.lt.s $f3, $f4
• Branch on FP condition code true or false
– bc1t, bc1f
• e.g., bc1t TargetLabel
Modified by S. J. Fritz Spring 2009 (53)
FP Example: °F to °C
• C code:
float f2c (float fahr) {
return ((5.0/9.0)*(fahr - 32.0));
}
– fahr in $f12, result in $f0, literals in global memory
space
• Compiled MIPS code:
f2c: lwc1
lwc2
div.s
lwc1
sub.s
mul.s
jr
$f16,
$f18,
$f16,
$f18,
$f18,
$f0,
$ra
Modified by S. J. Fritz Spring 2009 (54)
const5($gp)
const9($gp)
$f16, $f18
const32($gp)
$f12, $f18
$f16, $f18
FP Example: Array Multiplication
• X=X+Y×Z
– All 32 × 32 matrices, 64-bit double-precision elements
• C code:
void mm (double x[][],
double y[][], double z[][]) {
int i, j, k;
for (i = 0; i! = 32; i = i + 1)
for (j = 0; j! = 32; j = j + 1)
for (k = 0; k! = 32; k = k + 1)
x[i][j] = x[i][j]
+ y[i][k] * z[k][j];
}
– Addresses of x, y, z in $a0, $a1, $a2, and
i, j, k in $s0, $s1, $s2
Modified by S. J. Fritz Spring 2009 (55)
FP Example: Array Multiplication
• MIPS code:
li
li
L1: li
L2: li
sll
addu
sll
addu
l.d
L3: sll
addu
sll
addu
l.d
…
$t1, 32
$s0, 0
$s1, 0
$s2, 0
$t2, $s0, 5
$t2, $t2, $s1
$t2, $t2, 3
$t2, $a0, $t2
$f4, 0($t2)
$t0, $s2, 5
$t0, $t0, $s1
$t0, $t0, 3
$t0, $a2, $t0
$f16, 0($t0)
Modified by S. J. Fritz Spring 2009 (56)
#
#
#
#
#
#
#
#
#
#
#
#
#
#
$t1 = 32 (row size/loop end)
i = 0; initialize 1st for loop
j = 0; restart 2nd for loop
k = 0; restart 3rd for loop
$t2 = i * 32 (size of row of x)
$t2 = i * size(row) + j
$t2 = byte offset of [i][j]
$t2 = byte address of x[i][j]
$f4 = 8 bytes of x[i][j]
$t0 = k * 32 (size of row of z)
$t0 = k * size(row) + j
$t0 = byte offset of [k][j]
$t0 = byte address of z[k][j]
$f16 = 8 bytes of z[k][j]
FP Example: Array Multiplication
…
sll $t0, $s0, 5
addu $t0, $t0, $s2
sll
$t0, $t0, 3
addu $t0, $a1, $t0
l.d
$f18, 0($t0)
mul.d $f16, $f18, $f16
add.d $f4, $f4, $f16
addiu $s2, $s2, 1
bne
$s2, $t1, L3
s.d
$f4, 0($t2)
addiu $s1, $s1, 1
bne
$s1, $t1, L2
addiu $s0, $s0, 1
bne
$s0, $t1, L1
Modified by S. J. Fritz Spring 2009 (57)
#
#
#
#
#
#
#
#
#
#
#
#
#
#
$t0 = i*32 (size of row of y)
$t0 = i*size(row) + k
$t0 = byte offset of [i][k]
$t0 = byte address of y[i][k]
$f18 = 8 bytes of y[i][k]
$f16 = y[i][k] * z[k][j]
f4=x[i][j] + y[i][k]*z[k][j]
$k k + 1
if (k != 32) go to L3
x[i][j] = $f4
$j = j + 1
if (j != 32) go to L2
$i = i + 1
if (i != 32) go to L1
Interpretation of Data
The BIG Picture
• Bits have no inherent meaning
– Interpretation depends on the instructions
applied
• Computer representations of numbers
– Finite range and precision
– Need to account for this in programs
Modified by S. J. Fritz Spring 2009 (59)
• Parallel programs may interleave
operations in unexpected orders
– Assumptions of associativity may fail
(x+y)+z
x+(y+z)
-1.50E+38
x -1.50E+38
y 1.50E+38 0.00E+00
z
1.0
1.0 1.50E+38
1.00E+00 0.00E+00
• Need to validate parallel programs under
varying degrees of parallelism
Modified by S. J. Fritz Spring 2009 (60)
§3.6 Parallelism and Computer Arithmetic: Associativity
Associativity
• Originally based on 8087 FP coprocessor
– 8 × 80-bit extended-precision registers
– Used as a push-down stack
– Registers indexed from TOS: ST(0), ST(1), …
• FP values are 32-bit or 64 in memory
– Converted on load/store of memory operand
– Integer operands can also be converted
on load/store
• Very difficult to generate and optimize code
– Result: poor FP performance
Modified by S. J. Fritz Spring 2009 (61)
§3.7 Real Stuff: Floating Point in the x86
x86 FP Architecture
x86 FP Instructions
Data transfer
Arithmetic
Compare
Transcendental
FILD mem/ST(i)
FISTP mem/ST(i)
FLDPI
FLD1
FLDZ
FIADDP
FISUBRP
FIMULP
FIDIVRP
FSQRT
FABS
FRNDINT
FICOMP
FIUCOMP
FSTSW AX/mem
FPATAN
F2XMI
FCOS
FPTAN
FPREM
FPSIN
FYL2X
mem/ST(i)
mem/ST(i)
mem/ST(i)
mem/ST(i)
• Optional variations
–
–
–
–
I: integer operand
P: pop operand from stack
R: reverse operand order
But not all combinations allowed
Modified by S. J. Fritz Spring 2009 (62)
Streaming SIMD Extension 2 (SSE2)
• Adds 4 × 128-bit registers
– Extended to 8 registers in AMD64/EM64T
• Can be used for multiple FP operands
– 2 × 64-bit double precision
– 4 × 32-bit double precision
– Instructions operate on them
simultaneously
• Single-Instruction Multiple-Data
Modified by S. J. Fritz Spring 2009 (63)
• Left shift by i places multiplies an integer by 2i
• Right shift divides by 2i ?
– Only for unsigned integers
• For signed integers
– Arithmetic right shift: replicate the sign bit
– e.g., –5 / 4
• 111110112 >> 2 = 111111102 = – 2
• Rounds toward –∞
– c.f. 111110112 >>> 2 = 001111102 = +62
Modified by S. J. Fritz Spring 2009 (64)
§3.8 Fallacies and Pitfalls
Right Shift and Division
Who Cares About FP Accuracy?
• Important for scientific code
– But for everyday consumer use?
• “My bank balance is out by 0.0002¢!” 
• The Intel Pentium FDIV bug
– The market expects accuracy
– See Colwell, The Pentium Chronicles
Modified by S. J. Fritz Spring 2009 (65)
• ISAs support arithmetic
– Signed and unsigned integers
– Floating-point approximation to reals
• Bounded range and precision
– Operations can overflow and underflow
• MIPS ISA
– Core instructions: 54 most frequently used
• 100% of SPECINT, 97% of SPECFP
– Other instructions: less frequent
Modified by S. J. Fritz Spring 2009 (66)
§3.9 Concluding Remarks
Concluding Remarks
Examples
• References for Two’s Complement notation
• http://www.duke.edu/~twf/cps104/twoscomp.html
• http://en.wikipedia.org/wiki/Two's_complement
• http://mathforum.org/library/drmath/sets/select/dm_twos_co
mplement.html
• http://www.fact-index.com/t/tw/two_s_complement.html
• http://www.hal-pc.org/~clyndes/computerarithmetic/twoscomplement.html
• http://www.vb-helper.com/tutorial_twos_complement.html
• http://web.bvu.edu/faculty/traylor/CS_Help_Stuff/Two's%20
Complement.htm
Modified by S. J. Fritz Spring 2009 (67)
More Examples
Some
conversion
examples examples
• Some
conversion
http://people.csail.mit.edu/u/h/hammond/public_html/teaching/cs1001/
•2Comp.html
http://people.csail.mit.edu/u/h/hammond/publi
Internal
representation
c_html/teaching/cs1001/2Comp.html
http://www.cs.angelo.edu/~egarcia/lab22.html
• Internal representation
• http://www.cs.angelo.edu/~egarcia/lab22.html
Modified by S. J. Fritz Spring 2009 (68)