Transcript Computer Organization

Computer Organization
Chapter 2: Machine Instructions
and Programs
Department of CSE, SSE Mukka
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VTU NOTES
Memory Location and Addresses

In memory of computer, there are
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Number and character operands
Instructions
Memory consists of
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Millions of storage cells,
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Each cell can hold a bit ( 0 or 1 ) of information
So each bit can hold a very small amount of information
Memory is organized so that a group of n bits can be
stored or retrieved in a single, basic operation
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Each group of n bits is referred to as word
n is called as wordlength
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VTU NOTES
n bits
first word
second word
•
•
•
i th word
•
•
•
last word
Memory words.
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VTU NOTES
Contd…
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Range of word length of modern computers
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16 to 64 bits
Group of 8 bits referred to a byte
If the word length is 32 bits
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A single word can store a 32-bit 2’s complement number
Or
Four ASCII characters
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As shown in the figure
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
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VTU NOTES
32 bits
b1
•
•
•
b31 b30
b0
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers
(a) A signed integer
8 bits
8 bits
8 bits
8 bits
ASCII
character
ASCII
character
ASCII
character
ASCII
character
(b) Four characters
Examples of encoded information in a 32-bit word.
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VTU NOTES
Addresses

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Access to memory to store or retrieve a single item of
info ( either a byte or a word ) requires distinct names or
addresses for each item location
normally used addresses => 0 to 2k -1 as addresses of
successive memory locations
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The 2k addresses constitute address space of the computer
24-bit address generates an address space of 224 locations =
16M locations
32-bit ?
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VTU NOTES
Byte Addressability
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A byte is always 8-bit
Word length ranges from 16 to 64 bits.
Impractical to assign distinct addresses to individual bit
locations
Most practical?
Byte-addressable memory
Byte locations have addresses 0,1,2,..
If the word length of the machine is 32-bits, then
successive words are located at addresses ?
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VTU NOTES
Big-Endian and Little-Endian Assignments
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2 ways byte addresses can be assigned across words
Big-endian when
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Little-endian when
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Lower byte addresses for more significant bytes (leftmost
bytes ) of the word.
Lower bytes addresses used for less significant bytes (right
most bytes ) of the word.
In both cases 0,4,8 .. are taken as addresses of successive
words in the memory
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VTU NOTES
Word
address
Byte address
Byte address
0
0
1
2
3
0
3
2
1
0
4
4
5
6
7
4
7
6
5
4
•
•
•
k
2 -4
k
2 -4
k
2 -3
•
•
•
k
2- 2
k
2 - 1
k
2 - 4
(a) Big-endian assignment
k
2- 1
k
2 - 2
k
2 -3
k
2 -4
(b) Little-endian assignment
Byte and word addressing.
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VTU NOTES
Word Alignment
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Words are said to be aligned in memory if they begin at a
byte address that is a multiple of the number of bytes in a
word
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Eg : if wordlength is 16bits, aligned words begin at byte
addresses 0,2,4,….
If word length is 32 bits, aligned words begin at 0,4,8 etc…
If the words don’t begin at byte address that is a multiple
of no of bytes in the word, then words are said to have
unaligned addresses
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VTU NOTES
Accessing numbers, characters and strings
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Number
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Character
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By its word address as it usually occupies one word
By byte address
Strings
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They are of variable length
Beginning of the string by giving the beginning byte address which
contains first character
Successive bytes contains successive characters
Termination?
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Either by a special control character
Or a separate memory word location/ register containing a number
indicating the string length
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VTU NOTES
Problems
1.
2.
3.
Given that a memory has 32-bit address & is byteaddressable, what is the size of the memory(in bytes)?
Given that a memory has 24-bit address & is wordaddressable with a word length of 32 bits, what is the
size of the memory(in bytes)?
Given that a memory has 16-bit address and is byte
addressable. Word length is 32 bits. How many words
can we store in such a memory?
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VTU NOTES
Answers
1.
2.
3.
4GB
64MB
16K words
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VTU NOTES
Memory Operations
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Both program instructions and data operands are stored
in memory
To execute an instruction
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Processor control circuits must cause the word(s) containing
the instruction to be transferred from the memory to the
processor
Operands and results must also be moved between memory
and the processor
Two basic operations involving the memory
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Load ( or Read or Fetch )
Store ( or Write )
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VTU NOTES
Memory Operations –
LOAD operation
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Load transfers a copy of the contents of a specific
memory location to the processor
The memory contents remain unchanged
To start a load operation
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Processes sends the address of the desired location to
memory
Request that its contents be read
The memory reads the data and sends to the processor
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VTU NOTES
Memory operations Store operation
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Store operation transfers an item of information from the
processor to a specific memory location
Destroys the former contents of that memory location
Processor needs to send the address of the desired
memory location and also the data to be written into
that location
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VTU NOTES
Instructions and Instruction Sequencing
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Tasks that are carried out by a computer consists of a
sequence of small steps
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Eg., add two numbers, test for a particular condition, read a
character from keyboard, display a character on screen
A computer must have instructions capable of performing
four types of operations
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Data transfers between the memory and the processor
registers
Arithmetic and logic operations on data
Program sequencing and control
I/O transfers
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VTU NOTES
Register transfer notation
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Used to describe transfer of information from one location in
the computer to another
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To identify a location
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Possible locations are memory locations, processor registers, and
registers in the I/O subsystem
Symbolic name standing for its hardware binary address
Eg., name of memory locations – LOC,A,VAR2 etc
Name of registers – R0,R5
Name of I/O registers – DATAIN
Contents of a location denoted by placing square brackets
around the name
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R1  [LOC] means contents of memory location LOC are
transferred into processor register R1
R3  [R1] + [R2] ?
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VTU NOTES
Assembly language notation
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Used to represent machine instructions and programs
Example
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To perform the data transfer R1 [LOC] the statement is
Move LOC,R1
Old contents of register R1 are overwritten but contents of
LOC unchanged
R3  [R1] + [R2] is denoted by statement ?
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VTU NOTES
Basic Instruction Types
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A high level language program command C = A + B adds
the contents of variables A and B and stores the result in
variable C
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After compilation, the three variable A,B and C are assigned
distinct locations in memory
The contents of these locations represent the value of the
three variables
The action is C  [A] + [B]
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Contents of A and B locations are fetched from memory and
transferred into processor where the computation is
performed
Result is then sent back to the location C
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VTU NOTES
Accomplish C=A+B using Single Machine
Instruction
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The instruction contains memory addresses of 3 operands –
A,B and C
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Add A,B,C
A and B are source operands
C is destination operand
Add is the operation to be performed
Operation Source1,Source2, Destination
If k bits are needed to specify memory address of each
operand
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In addition to the bits needed to denote Add operation we need 3k
bits more
For a modern processor with 32-bit address space,a 3-address
instruction is too large to fit in one word for a reasonable
wrodlength
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VTU NOTES
Accomplish C = A + B using two-address
instructions
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Operation Source, Destination
Eg., Add A,B which performs the operation B  [A] + [B]
When sum is calculated result is sent to memory replacing
original contents of location B
We cannot use a single two-address instruction as we don’t
want to destroy the contents of A or B
Solution?
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Use a instruction which copies contents of one memory location to
another
Move B,C performs the operation C  [B] leaving contents of B
unchanged
Actually it only “copies” not “moves”
Final solution is
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Move B,C
Add A,C
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VTU NOTES
Accomplish C = A + B using one-address
instructions
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Even two-address instructions will not fit into one single word
of memory
Use one-address instruction
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Second operand , whenever required, is present in a unique location
Eg., usage of accumulator, a processor register
Add A
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Load A
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Copies contents of memory location A into accumulator
Store A
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means Add the contents of memory location A to the contents of
accumulator register and place the sum back into the accumulator
Copies contents of accumulator to memory location A
Solution?
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VTU NOTES
Contd…
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Load A
Add B
Store C
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Operand specified may be source or destination depending on
the instruction
For load it is source,
For store it is destination
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VTU NOTES
Accomplish C = A + B using one-address
instructions, and General purpose registers
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Most modern computers have 32 General Purpose
Registers or more
Only 5 bits sufficient to address 32 GPRs. How?
Registers are used to store data temporarily
Since access time to registers is much less than memory
frequent access to memory is reduced hence enhancing
speed
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VTU NOTES
Accomplish C = A + B using one-address
instructions, and General purpose registers
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If Ri is a GPR
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Data transfer instruction - Move
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Load A,Ri
Store Ri,A
Add A,Ri are generalizations for the single-accumulator case
When we want to move from one place to another.
A single instruction Move can be used in place of Load
and Store
Move Source, Destination
Move A, Ri is same as Load A,Ri
Move Ri,A is same as Store Ri,A
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VTU NOTES
Contd
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If artihmetic operations are allowed only on operands in
processor registers then to achieve C = A + B
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Move A,Ri
Move B,Rj
Add Ri,Rj
Move Rj,C
If one operand can be in memory but other must be in
register then
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Move A,Ri
Add B,Rj
Move Rj,C
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VTU NOTES
Zero-Address instructions
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Locations of all operands defined implicitly
Machines which store operands in a structure called
pushdown stack
Instructions does not specify any memory address
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VTU NOTES
Instruction execution and straight line
sequencing
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Assumptions
Begin execution here
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Address
i
i +4
i +8
GPRs
One addr insts
A
Wordlength 32bits
Byte addressable B
Full address in
Contents
Move
Add
Move
A,R0
B,R0
R0,C
C
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Single word instruction
The three insts Figure
at 2.8. A program for C  [A] + [B].

i, i + 4, i + 8
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VTU NOTES
3-instruction
program
segment
Data for
the program
Instruction execution and straight line
sequencing
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PC holds address of instruction to be executed next
To begin execution
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place the address of first inst to be executed in PC
Processor control circuits use info in PC to fetch and execute
instructions, one at a time, in order of increasing addresses
This is called as Straight-line sequencing
During the execution of each instruction, PC is incremented by
4
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VTU NOTES
Instruction execution and straight line
sequencing
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Execution is two phase
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Instruction Fetch
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Instruction Execute
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Instruction is fetched from memory location whose address in PC
This instruction is placed in IR
IR is examined to determine which operation is to be performed
Specified operation is then performed by processor
Involves fetching operands from memory or processor registers,
performing arithmetic or logic operations, storing results in
destination
At some point during this two-phase, the contents of PC is
advanced to point to next instruction
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VTU NOTES
Branching
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Branch instruction load a new value to PC than the
address of next immediate instruction following the
branch instruction
This new address is called branch target
A conditional branch instruction causes branch only if a
specified condition is satisfied
Eg., Branch>0 LOOP
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VTU NOTES
Move
Add
Add
i
i + 4
i + 8
i + 4n - 4
i + 4n
SUM
NUM1
NUM2
NUM n
Figure 2.9.
Add
Move
NUM1,R0
NUM2,R0
NUM3,R0
•
•
•
NUM n ,R0
R0,SUM
•
•
•
•
•
•
A straight-line program for adding n numbers.
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VTU NOTES
Move
Clear
LOOP
Program
loop
N,R1
R0
Determine address of
"Next" number and add
"Next" number to R0
Decrement
Branch>0
Move
SUM
N
NUM1
NUM2
NUM n
Figure 2.10.
R1
LOOP
R0,SUM
•
•
•
n
•
•
•
Using a loop to add n numbers.
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VTU NOTES
Assignment to be submitted on Thursday
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Express the following signed numbers in 2’s
complement notation and perform addition and
subtraction. State whether overflow occurs or not
4-bit notation
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5-bit notation
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2&3, 5 & -6, -7 & 6, -8 & -3, 7 & 4
12 & 3, 7 & -7, -6 & 14, -10 & -4, 12 & 8
Represent the following numbers in 32-bit Bigendian and Little-endian memory organization
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81234561
-81234561
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VTU NOTES
Indirection and pointers
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Indirect mode – the Effective address of the operand is
the contents of a register or memory location whose
address appears in the instruction
The register of memory location that contains the
address of an operand is called a pointer
Analogy of treasure hunt
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
Instead of finding the treasure, we find the address where we
find the treasure
By changing the contents of register R1 or location A in the
following figure, the same add instruction fetches different
operands to add to register R0.
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VTU NOTES
Add
(R1),R0
Add
(A),R0
Main
memory
B
R1
Operand
B
Register
(a) Through a general-purpose register
A
B
B
Operand
(b) Through a memory location
Figure 2.11. Indirect addressing.
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VTU NOTES
Indirect addressing logic for the program of adding
n numbers using loop
Address
LOOP
Contents
Move
Move
Clear
Add
Add
Decrement
Branch>0
Move
N,R1
#NUM1,R2
R0
(R2),R0
#4,R2
R1
LOOP
R0,SUM
Initialization
Figure 2.12. Use of indirect addressing in the program of Figure
2.10.
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VTU NOTES
INDEXED ADDRESSING
Add
20(R1),R2
1000
1000
R1
20
R1
20 = offset
1020
Operand
(a) Offset is given as a constant
Add
1000(R1),R2
1000
20 = offset
1020
Operand
(b) Offset is in the index register
Figure 2.13. Indexed addressing.
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VTU NOTES
n
Student ID
Test 1
Test 2
N
LIST
LIST + 4
LIST + 8
LIST + 12
LIST + 16
Test 3
Student ID
Test 1
Test 2
Test 3
•
•
•
Figure 2.14. A list of students' marks.
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VTU NOTES
Student 1
Student 2
LOOP
Move
#LIST,R0
Clear
R1
Clear
R2
Clear
R3
Move
N,R4
Add
4(R0),R1
Add
8(R0),R2
A dd
12(R0),R3
Add
#16,R0
Decrement
R4
Branch>0
LOOP
Move
R1,SUM1
Move
Move
R2,SUM2
Note: contents of R0,
which is used as
indexed register, are not
changed when it is used
in indexed addressing
mode to access test
scores.
Contents of R0 change
only in last Add
instruction, to move
from one student
record to the next
R3,SUM3
Figure 2.15. Indexed addressing used in accessing test scores in the list in Figure
2.14.
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VTU NOTES
Indexed addressing contd…

Several variations of the basic form of indexed addressing
provide efficient access to memory operands
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A second register may be used to contain the offset X, called
as based indexed addressing mode
Denoted as ( Ri, Rj )
Effective address is the sum of contents of Ri and Rj
Second register is called base register.
Provides more flexibility to the user
Eg., suppose, in the previous example, instead of only 3 items,
each student record contain a large no of items, say k
We can replace the three Add instructions by a single
instruction inside a second loop
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VTU NOTES
Indexed addressing contd…
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
Problem
The list of student marks shown in prev figure 2.14, is changed
to contain j test scores for each student. Assume that there are
n students. Write an assembly language program for computing
the sums of the scores on each test and store these sums in
the memory word locations at addresses SUM, SUM + 4, SUM
+ 8,…. The number of tests, j, is larger than the number of
registers in the processor. Use two nested loops, the inner
loop should accumulate the sum for a particular test, and the
outer loop should run over the number of tests, j. assume that
j is stored in memory location J.
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VTU NOTES
Solution
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VTU NOTES
Indexed addressing mode contd..

based indexed addressing mode with offset



Uses two registers plus a constant
X( Ri, Rj ) - Effective address is the sum of the constant X and
the contents of registers Ri and Rj
This mode implements 3-Dimensional array
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VTU NOTES
Relative addressing
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

Till now for index mode, registers we used are general purpose registers
A useful variation of this is to use Program Counter PC instead of a
general purpose register
X(PC) – to address a memory location that is X bytes away from the
location presently pointed to by the program counter
Relative mode- the effective address is determined by the index mode using
the program counter in place of the general-purpose register Ri.
MOST common use is to specify the target address in branch instructions
 Eg., Branch>0 LOOP
 If branch condition is true, the program execution goes to branch target
location identified by name LOOP
 Can compute this location by specifying it as an offset from the current
value of the program counter.
 Since branch target address can be either before or after the branch
instruction, the offset is given as a signed number
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VTU NOTES
Example for relative addressing mode
Address

LOOP



Contents
Move
Move
Clear
Add
Add
Decrement
Branch>0
Move
N,R1
#NUM1,R2
R0
(R2),R0
#4,R2
R1
LOOP
R0,SUM
Initialization
Assume 4 instructions starting from LOOP are located at
memory locations 1000,1004,1008 & 1012.
Updated contents at the time branch target address is
generated is 1016. to branch to location LOOP(1000), the
offset value needed is X = -16
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VTU NOTES
Additional modes


Autoincrement and autodecrement mode – useful for
accessing data items in successive locations in the
memory
Autoincrement mode –


The effective address of the operand is the contents of a
register specified in the instruction. After accessing the
operand, the contents of this register are automatically
incremented to point to next element in the list
(Ri)+

The increment is 1 for byte-sized operands, 2 for 16-bit operands and
4 for 32-bit operands. Usually size of operand is specified in the
instruction
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VTU NOTES
Autoincrement addressing logic for the
program of adding n numbers using loop
LOOP
Move
Move
Clear
Add
Decrement
Branch>0
Move
N,R1
#NUM1,R2
R0
(R2)+,R0
R1
LOOP
R0,SUM
Initialization
Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.
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VTU NOTES
Autodecrement mode




The contents of a register specified in the instruction are
first automatically decremented and are then used as the
effective address of the operand
Denoted by –(Ri)
Operands are accessed in descending address order.
The way the autoincrement and autodecrement modes
are specified in very useful when implementing an
important data structure called a stack.

Always we can use two instructions to perform the
functionality of autoincrement and autodecrement mode
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VTU NOTES