Lecture 6 Instruction Set Architectures
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Transcript Lecture 6 Instruction Set Architectures
Topic 3a
Two’s Complement Representation
Introduction to Computer
Systems Engineering
(CPEG 323)
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2’s Complement
Number and its representation are not the
same thing!
Representation is a convention defined for
expressing the number.
A number may have different representations,
e.g. BCD, hexadecimal, 2’s complement, etc.
2’s complement: a kind of representation
defined as follows
Number
bn1 * (2
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n1
Representation
n 2
) (bi * 2i )
i 0
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bn-1 bn-2 ……b1b0
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Excercises
What is 2’s complement representation
of +3 ?
Answer: +3 = 0011 => + 3 = 0x(-2^3) + 0011 = 011
How about 2’s complement representation of -3 ?
Answer: -3 = -(0011) => - 3 => 1x(-2^3) + 0011 = -5 => 1101
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2’s Complement
n 2
bn1 * (2n1 ) (bi * 2i )
i 0
0
1
2
3
4
5
6
7
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bn-1 bn-2 ……b1b0
0000
0001
0010
0011
0100
0101
0110
0111
-8
-7
-6
-5
-4
-3
-2
-1
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1000
1001
1010
1011
1100
1101
1110
1111
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Signed Integers(2’s Complement)
(For 4 bits)
-1
-2
-3
1111
1110
Reference: Katz: Contemporary
Logic Design, p243
+0
0000
+1
0001
1101
0010
-4
1100
0011
+3
-5
1011
0100
+4
-6
1010
0101
1001
-7
0110
1000
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+2
0111
+7
+6
+5
Why 1111 and 0000 are
adjacent?
What is the meaning of bit 3?
What is the sign of 0?
What is the smallest number?
What is the biggest number?
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2’s Complement (Cont.)
Representing a negative number –x
From the representation of x to that of –x
Number
x
-x
Representation
bn-1 bn-2 ……b1b0
bn-1bn-2 ……b1b0
Invert each bi, then
add 1
Proof of correctness: an exercise!
Shortcut: Invert every bit and add 1 to the least
significant bit
Example: - (0100) = 1011 + 1 = 1100
Example: 10010 = 01100100 10011100 = -10010
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Fit a shorter number to longer bits
Why is it necessary?
Compare an integer with a long integer:
typecasting
Load a byte to a word
To add an immediate field to a 32-bit number
MIPS ALU only works with values in 32-bit
registers
How to deal with smaller sizes?
What about larger sizes?
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Fit a shorter number to longer bits
Example (2-bit): 10= 1 *(-21)+0 *20=-210
Representing -210 in 4-bit word: Can you do
that? What is the intuition?
copy the sign bit into the other bits (sign
extension)
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0010
-> 0000 0010
1010
-> 1111 1010
Proof? Are 1010 = 1111 1010 ?
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Addition & Subtraction
Addition: Just like in grade school
0110
+ 0001
Substraction: a-b=a+(-b)
Two's complement operations easy
0111-0110= 0111
+1010
1 1
1 0 0 01
So 0111-0110= 0001
Have you specially handled the sign bits?
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Addition & Subtraction (Cont.)
Wait! There is one extra bit lost!
0111-0110= 0111
+1010
1 1
10001
Why the 1 can be omitted?
is
Because
0*23
+ 1*(-23)
1*23
0
But treated in the addition as
0*23
+ 1*23
1*23
10
1-1=1+1=0 from the viewpoint of 1-bit.
So as long as you do not consider the carry brought by
1+1 (the green 1), cpeg323-08F\Topic3a-323
you are right!
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Addition & Subtraction (Cont.)
Questions:
Do you have an adder and a “subtractor”?
What about unsigned numbers? (Another
adder?)
Advantage of using 2’s complement
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Sub can share the same logic as add
Sign bit can be treated as a normal number bit
in addition.
These are the clever points!
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Overflow
Addition:
0111
+ 0110
overflow!
1111
+1000
Overflow!
What is the sign of the input?
What is the sign of the output?
Can overflow occur in adding a positive and a
negative number?
Can overflow occur with 0?
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Consider the operations A + B, and A – B
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Overflow
Addition:
0111
+ 0110
1101
1111
+ 1000
10111
What is the sign of the input?
What is the sign of the output?
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Detecting Overflow
Overflow occurs when:
add two positives yields a negative
add two negatives gives a positive
or, subtract a negative from a positive and get
a negative
or, subtract a positive from a negative and get
a positive
What about addition and subtraction of
unsigned numbers?
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What should CPU do about
overflow?
Ignore it?
Don't always want to detect overflow
Addu, addiu, subu (MIPS: do not generate a overflow)
Generate a trap so that the programmer can try
to deal with it?
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An exception (interrupt) occurs
Control jumps to predefined address for exception
Interrupted address is saved for possible resumption
Add, sub
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Instructions
Comparison
Unsigned numbers
sltu: set on less than unsigned
sltiu: set on less than immediate unsigned
Signed numbers
slt: set on less than
slti: set on less than immediate
Example: What are the values of $t0 and $t1?
$s0= 1111 1111 1111 1111 1111 1111 1111 1111
$s1= 0000 0000 0000 0000 0000 0000 0000 0001
(1) slt $t0, $s0, $s1 (2) sltu $t1, $s0, $s1
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Example (cont’d)
What are the values of $s0 and $s1?
$s0= 1111 1111 1111 1111 1111 1111 1111 1111
$s1= 0000 0000 0000 0000 0000 0000 0000 0001
Answer:
slt $t0, $s0, $s1 -- the result of $t0 is 1 if both are signed
sltu $t1, $s0, $s1 -- the result of $t1 is 0 if both are unsigned
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Instructions (Cont.)
Load/Store
lb: load byte
lbu: load byte unsigned
Example:
lb $s1, 100($s2)
What is the values of $s1
memory[$s2+100] = 0000 0000?
When memory[$s2+100] = 0000 0001?
When memory[$s2+100] = 1111 1111?
When
Example:
lbu $s1, 100($s2)
What is the values of $s1
when memory[$s2+100] = 1111 1111?
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Remarks
MIPS 4000 has "Integer Arithmetic
Overflow“ exception.
For most of the processors today,
integer overflow will not trigger
interrupt. Instead, some status bits will
be set such that software may detect
such situation.
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Remarks (cont’d)
Usually, a typical architecture may have status bits like
N - not zero
Z - zero
S - sign
O – overflow
The 4 bits make 16 combinations. They can be used to
represent 16 situations (for compare and conditional branch),
which includes:
signed: >=, =, <=, !=
unsigned: >=, =, <=, !=
integer overflow, underflow, and etc.
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