Transcript Lab 3 : Multiplier

Adders and Multipliers
Review
ARITHMETIC CIRCUITS
• Is a combinational circuit that performs
arithmetic operations, e.g.
– Addition
– Subtraction
– Multiplication
– Division
with numbers in binary form.
Half Adder
• Generates the sum of 2 binary digits.
X
Sum = X  Y
Y
Cy = X.Y
Truth Table of Half Adder
Logic Diagram of Half Adder
Full Adder
• Forms the arithmetic sum of 3 input bits.
X
Y
Cin
Sum = X  Y  Z
Cout = X.Y + Z (X  Y)
Truth Table of Full Adder
K-Maps for Full Adder
Full Adder
• A Full Adder can also be implemented
using 2 HALF ADDERS and one OR
gate.
– Cascade two half adders
(Array method)
Full Adder (Array Method)
Lab 3 : Multiplier
Overview
2-bits x 2-bits Multiplier
Terms
2
X 3
-------------6
Mutiplicand
Multiplier
Product
Multiplication in binary form?
1. Rewrite the multiplication in binary
form.
2. Sketch the black box view.
3. The multiplier multiplies two __?__
bits numbers.
2-bits x 2-bits Multiplier Design
• Two techniques:
–Using the standard K-Map
–Using Arrays (cascaded
approach)
Part A: Using the K-Map Technique
• Sketch the back box.
• Sketch the Truth Table for a 2-bit “multiplier” and
2-bit “multiplicand”.
– Input (Multiplier) = A1 and A0
– Input (Multiplicand) = B1 and B0
– Output (4-bits) = S3, S2, S1 and S0 or
S[3..0]
• Using K-Maps, obtain the boolean expression
for each output.
• Sketch the schematic diagram.
Lab 3 Requirement
• Simulate your design
– Input A1 and A0 = counting sequence.
– Input B1 and B0 = a fixed value.
• Study this waveform
LAb 3
• Transfer in Max+Plus II using the
Graphic Editor.
• Verify your design.
• Submit : Truth Table, K-Maps,
Boolean Expressions, Printed:
Schematic and Waveform results
Part B: Using the Array (Cascaded)
Technique
• Create the 2x2 multiplier using Full
ADDERS.
… tHE cONcEpt
A1 A0
x B1 B0
C
S3
C
A1B0 A0B0
+ A1B1 A0B1
S2
S1
S0
A 2-Bit by 2-Bit Binary Multiplier
AND
computes
A0 B0
Half adder
computes
sum. Will
need FA for
larger
multiplier.
In Lab 3 …
• Simulate your design
– Input A1 and A0 = counting sequence.
– Input B1 and B0 = a fixed value.
… in LAb 3
• Transfer in Max+Plus II using the
Graphic Editor.
• Verify your design.
• Submit : Truth Table, K-Maps,
Boolean Expressions, Printed:
Schematic and Waveform results
Part C: 4-bits x 4-bits
Multiplier
Using Array 2x2
Basic Idea of a Larger Multiplier
(4-bits by 3-bits)
Multiplier Product
• The product of m-bit x n-bit
numbers is an (m+n)-bit number.
=> The product of two 4-bit
numbers is an 8-bit number.
How about this one?
13
X 11
-------------143
Mutiplicand
Multiplier
Product
1
1
0
1
(13) multiplicand
1
0
1
1
(11) multiplier
1
1
0
1
1
1
0
1
0
0
0
0
1
1
0
1
0
0
0
1
X
1
1
Partial products
1
1
(143) Product
S7
A3
A2
A1
A0
B3
B2
B1
B0
A 3B 0
A 2B 0
A 1B 0
A 0B 0
A 3B 1
A 2B 1
A 1B 1
A 0B 1
A 3B 2
A 2B 2
A 1B 2
A 0B 2
A 3B 3
A 2B 3
A 1B 3
A 0B 3
S6
S5
S4
S3
S2
S1
S0
From the previous slide:
1. The multiplier multiplies two __?__ bits
numbers.
2. Sketch the black box view.
In Lab 3
• Design a 4-bits x 4-bits multiplier using the
Array (cascaded) technique, by utilizing:
– The 2-bits x 2-bits Multiplier and full
adder designed earlier.
• Hints : Look back at the concept of 2x2
multiplier. Take the same step.
… in LAb 3
• Transfer in Max+Plus II using the
Graphic Editor.
• Verify your design.
• Submit (Printed) - Schematic, and
Waveform results
4x4 Combinational Multiplier
Note use of parallel carry-outs to form higher order sums
12 Adders, if full adders, this is 6 gates each = 72 gates
16 gates form the partial products
total = 88 gates!
Array Multiplier
1 building block
4 x 4 array of building blocks
Extra Lab Activity
• Modify your design so that the
output of your multiplier could
be observed on two 7-segment
displays on the UP2 board.
• Download your 4-bits x 4-bits
multiplier design to the UP2
board.
Part C : 4 x 4 Multiplier
Extra Activity
• Download your 4x4 multiplier to UP2 board
using FPGA (Flex10K)
Pin Configuration to input
(use flex switch 1-8)
A0
A1
A2
A3
B0
B1
B2
B3
4x4
Multiplier
(your design)
Pin Configuration to output
(use flex digit 1 & 2 )
Tenth & Unit
Segment
Decoder
7447
BCD to
7Seg
a-g
7447
BCD to
7Seg
a-g
Max+PlusII Tips
• Bus line
A3
A2
A1
A0
A[3..0]
~ GOOD UCK !!