Transcript Metal-Oxide-Semiconductor Fields Effect Transistors (MOSFETs)

COE 360
Principles of VLSI
Design
Conduction in Semiconductors
Fermi Level
MOS
Inverter
Terminology
donor: impurity atom that increases n
acceptor: impurity atom that increases p
n-type material: contains more electrons than holes
p-type material: contains more holes than electrons
majority carrier: the most abundant carrier
minority carrier: the least abundant carrier
intrinsic semiconductor: n = p = ni
extrinsic semiconductor: doped semiconductor
Remember
Type
n
p
Pure
intrinsic
ni
ni
Donor, Group-5, ND
n- type
ND
ni 2/ND
Acceptor, Group-3, NA
p- type
ni 2/NA
NA
ND + NA but ND > NA
n- type
n=ND - NA
ni 2/n
ND + NA but NA > ND
p- type
ni 2/p
p=NA – ND
ND + NA but ND = NA
intrinsic
ni
ni
3
Remember
1
1


qn n  qp p qp p
1
1


qn n  qp p qn n
L
Rρ
A
I
J
A
p - type
n - type

1

4
Fermi level
For intrinsic semiconductors, the Fermi level EF, is in the
middle of the energy gap and it is called intrinsic Fermi-level
Ei.
EC
Conduction Band
EF = Ei
EV
Energy
Gap
Valence Band
This is an energy level in the energy gap that
represents the point where the probability of finding an
electron is = 0.5 .
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Fermi level
N-type
For N-type semiconductors, EF is closer to conduction band EC.
 F = Fermi potential = (EF - Ei)/q = Vtln(ND/ni)
Vt ≈ 0.025 V
Conduction Band
Ei
q
EC
EF
F
Valence Band
Valence Band
EV
N-type
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Fermi level
P-type
For P-type semiconductors, EF is closer to Valence Band EV.
 F = (EF - Ei)/q =-Vtln(NA/ni)
Conducting Band
Conduction Band
EC
Ei
q
F
EF
Valence
Band
Valence
Band
EV
P-type
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Fermi level
• As doping level increases, Fermi level moves
closer to valence band in p-type and to conduction
band in n-type as shown
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9
10
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Built-in Voltage in P-N Junction (Diode)
Vbi =  FN –  FP
kT  Na  kT  Nd 
Vbi 
ln  
ln 
q  ni  q  ni 


built-in voltage  Vbi  kT ln Na Nd 
q  ni 2 
Na acceptor level on the p side
Nd donor level on the n side
Vbi is typically ≈ 0.5 V to 0.8 V
Example
• Find the built-in voltage for a Si p-n
junction with NA = 1015 cm-3 and ND= 1017
cm-3
Assume ni = 1010 cm-3 and KT/q ≈ 0.025 V
Vbi
kT  N A N D

ln
2
q
n
i

15
17

10
x
10
  0.025 ln(
)
10 2

(10 )

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COE 360
Principles of VLSI
Design
Metal Oxide Semiconductor
MOS
Introduction
•
A MOS (Metal Oxide Semiconductor) is a semiconductor
device.
• MOS - name is derived from its physical structure
• Small size
• Requires low power
• Implement digital & analog functions very large scale Integrated
(VLSI) circuit
•
A MOS transistor is a voltage controlled switch. (Moor’s law)
Physical structure of the enhancement-type NMOS transistor:
Physical structure of the enhancement-type NMOS transistor
Device Structure
• Four terminals
–
–
–
–
• L
W
tox
Source (S)
Gate (G)
Drain (D)
Body (B)
Length of channel region
Width of the substrate
Thickens of an oxide Layer
Schematic structure of MOSFET
MOS
• In a MOS device, a voltage is applied to a metal
layer, which pushes away mobile carriers in a
semiconductor layer.
• The metal is separated from the semiconductor by
an insulating layer, usually an oxide.
Metal
Oxide
Semiconductor
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N and P channel of Metal Oxide Field
Effective Transistor (MOSFET)
•
If the MOSFET is an n-channel or NMOS, then the
source and drain are 'n+' regions and the body is a 'p'
region.
•
If the MOSFET is a p-channel or PMOS, then the
source and drain are 'p+' regions and the body is a 'n'
region.
MOSFET : Metal Oxide Semiconductor Field Effect
Transistors
Structure: n-channel MOSFET
(NMOS)
body
B
source
S
gate
G
IG=0
drain
D
ID=IS
IS
metal
oxide
n+
n+
p
L
W
NMOS (N-Channel Metal Oxide Semiconductor)
gate
source
metal
n-type
metal
oxide insulator
drain
metal
n-type
p-type
metal
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Circuit Symbol (NMOS)
D
ID= IS
G
B
IG= 0
IS
S
(IB=0, should be reverse biased)
VGS = 0
n+pn+ structure  ID = 0
body
B
source
S
gate
G
- +
drain
D
VD>Vs
metal
oxide
n+
n+
p
L
W
0 < VGS < Vt (threshold voltage)
n+-depletion-n+ structure  ID = 0
body
B
source
S
gate
G
- +
drain
D
VD>Vs
+++
metal
oxide
n+
n+
p
L
W
NMOS transistor with a positive voltage applied to the
gate. An n channel is induced at the top of the substrate
beneath the gate.
VGS > Vt
n+-n-n+ structure  ID > 0
body
B
source
S
n+
gate
G
- +
+++
+++
+++
metal
oxide
----p
L
drain
D
VD>Vs
n+
W
NMOS Transistor Channel
VGS > VTH(n)
gate
- +
source
metal
n-type
+ + +
_
_
metal
oxide insulator
e e_ e _ e_ e _
_
drain
metal
n-type
+ + +
_
_
p-type
h
h
h
h
h
h
h
h
h
h
metal
When VGS is larger than a threshold voltage VTH(n), the attraction to the gate is so
great that free electrons collect there.
The applied VGS creates a channel under the gate (an area with free electrons).
Now current can flow if there is a voltage from the source to the drain.
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NMOS Transistor Circuit Symbol
VDS
- +
VGS
- +
source
drain
gate
ID
IG
metal
oxide insulator
metal
n-type
metal
n-type
p-type
metal
G
IG
ID
S
-
VDS + D
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NMOS Operation
• Vt is the threshold voltage
• If VGS < Vt, then there is insufficient positive charge
on the gate to invert the p-type region
– This is called “cut-off”
• If VGS> Vt, then there is sufficient charge on the gate
to attract electrons and invert the p-type region,
creating an n-channel between the source and drain
– The MOSFET is now “on”
– 2 modes of operation: linear and saturation
Linear Region
A voltage-controlled resistor @small VDS
B
S
D
- +
+++
+++
metal
- oxide
- - -
n+
VGS1>Vt
ID
increasing
VGS
n+
p
B
S
D
-+
+++
+++
+++
metal
- -oxide
- - --
n+
VGS2>VGS1
G
n+
p
cut-off
B
S
n+
D
-+
+++
+++
+++ +++
metal
- - -oxide
-----p
VDS
0.1 v
VGS3>VGS2
n+
Increasing VGS puts more
charge in the channel, allowing
more drain current to flow
Saturation Region
occurs at large VDS
The saturation region is when the MOSFET
experiences pinch-off.
Pinch-off occurs when VG - VD is less than Vt.
body
B
source
S
gate
G
-
+
drain
D
VD>>Vs
+++
+++
+++
metal
oxide
n+
n+
p
Saturation Region
once pinch-off occurs, there is no further increase in
drain current
VDS > VGS - Vt
body
B
source
S
gate
G
-
+
drain
D
VD>>Vs
+++
+++
+++
metal
oxide
n+
n+
p
Regions of operation
• Three regions of operation
– Cutoff
– Linear
– Saturation
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NMOS I-V Curves
ID linear mode
saturation mode
VGS = 3 V
VDS>VGS-Vt
VDS<VGS-Vt
VDS = VGS - Vt
cutoff mode (when VGS < VTH(N))
VGS = 2 V
VGS = 1 V
VDS
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Simplified MOSFET I-V Equations
Cut-off: vGS< Vt
iD = iS = 0
Linear: vGS>Vt and vDS < vGS-Vt
iD = kn’(W/L)[(vGS-Vt)vDS - 1/2vDS2]
Saturation: vGS>Vt and vDS > vGS-Vt
iD = 1/2kn’(W/L)(vGS-Vt)2
where kn’= (electron mobility)x(gate capacitance)
= n(eox/tox) …electron velocity = nE
and Vt depends on the doping concentration and gate
material used
PMOS Transistor
• Similar, but doping and voltages reversed
–
–
–
–
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
bulk Si
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MOS Transistor Types and Symbols
D
G
S
NMOS
D
G
S
PMOS
Transistors as Switches
• We can view MOS transistors as electrically
controlled switches
• Voltage at gate controls path from source to drain
d
nMOS
pMOS
g=0
g=1
d
d
OFF
g
ON
s
s
s
d
d
d
g
OFF
ON
s
s
40
s
COE 360
Principles of VLSI
Design
MOS Inverter
41
Review of Boolean Algebra
A Z
A B Z
A B Z
A B Z
A B Z
0
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
0
1
0
0
1
1
1
0
1
1
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
0
1
1
0
NOT
Truth Table
ZA
OR
Truth Table
Z  A B
AND
Truth Table
Z = AB
NOR
Truth Table
Z = A+ B
NAND
Truth Table
Z = AB
Logic Gate Symbols and Boolean
Expressions
MOS Devices
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Logic Voltage Level Definitions
• VIL – The maximum input voltage that will be
recognized as a low input logic level
• VIH – The minimum input voltage that will be
recognized as a high input logic level
• VOH – The output voltage corresponding to an input
voltage of VIL
• VOL – The output voltage corresponding to an input
voltage of VIH
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Inverter = NOT Gate
Vin
Vout
Ideal Transfer Characteristics
Vout
Vin
NMOS Inverter: Resistor Pull-Up
VDD
Circuit:
Voltage-Transfer Characteristic
vOUT
RD
iD
A
+
+
vIN
–
VDD
F
vDS = vOUT
–
0
A F
0 1
1 0
VDD
vIN
MOS Inverter - Resistor Load
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