Transcript AC-Coupled Charge Amplifier

Outcome from the VMM/sTGC
Workshop at Weizmann Institute
May 14-15, 2015
Gianluigi De Geronimo
Brookhaven National Laboratory, Upton, NY
Acknowledgement
Brigitte Vachon, Vladimir Smakhtin, Alex Vdovin, Nachman Lupu, Benoit Lefebvre,
George Mikenberg, Lorne Levinson, Daniel Lellouch, Venetios Polychronakos
1
May 22nd, 2015
Saturation Issue with TGC Sensors
2
from B. Lefebvre, V. Smakhtin and B. Vachon, April 2015
Saturation Issue with TGC Sensors
3
from B. Lefebvre, V. Smakhtin and B. Vachon, April 2015
Saturation Issue with TGC Sensors
4
from B. Lefebvre, V. Smakhtin and B. Vachon, April 2015
Saturation Issue with TGC Sensors
5
from B. Lefebvre, V. Smakhtin and B. Vachon, April 2015
Front-End Circuit
BLH
CA1
CA1 output
CA2
CA3
SH
adaptive resets
with PZ cancellation
Shaper output
CA1, CA2, CA3 provide charge (current) amplification before shaper
Amplification is required for noise, and it is programmable
6
from G. De Geronimo, December-April 2015
TGC 200pF 2pC
iin
2pC
Qin
CA1
CA2
CA3
out
7
500mV + tail
from G. De Geronimo, December-April 2015
TGC 200pF 4pC
iin
4pC
Qin
CA1
saturation
CA2
CA3
out
8
900mV no tail
baseline tail (several µs)
from G. De Geronimo, December-April 2015
Dual-Polarity Charge Amplifier
sn
1
Ibias
from
sensor
Qin
N
sn
CF·N
CF
sp
Qout = Qin ·N
-∞
sn
sp
Ibias
1
9
sp
N
from G. De Geronimo, December-April 2015
to virtual
ground
τF Correction for Type 1 Dead Time
Output
2pC
Solution: CA time constant τF ~1/10 by
modifying size of feedback MOSFETs
in saturation deadtime limited to sub-µs
500 fC @ 200ns
CA1
10
from G. De Geronimo, December-April 2015
Origin of Type 2 Dead Time ?
11
from B. Lefebvre, V. Smakhtin and B. Vachon, April 2015
AC-Coupled Charge Amplifier
Ideal charge amplifier with AC-coupled charge signals
RDET = 10 MΩ
CAC = 100 pF
Charge signals
CDET = 100 pF
Ideal charge
amplifier
12
AC-Coupled Charge Amplifier
Response of charge amplifier to AC-coupled charge signals
ICAC (input current through CAC)
Charge amplifier output
t = RFCF
200µs
13
AC-Coupled Charge Amplifier
Response of charge amplifier to AC-coupled charge signals
Detail
ICAC (input current through CAC)
Charge amplifier output
t = RFCF
10µs
14
AC-Coupled Charge Amplifier
Response of charge amplifier to AC-coupled charge signals
Detail
ICAC (input current through CAC)
Transfer function =
sRDETCAC
1 + sRDET(CDet+CAC)
(derivative of exponential decay)
Charge amplifier output
10µs
15
AC-Coupled Charge Amplifier
Response of charge amplifier to AC-coupled charge signals
Detail
ICAC (input current through CAC)
Transfer function =
sRDETCAC
1 + sRDET(CDet+CAC)
t = RDET(CDet+CAC)
Charge amplifier output
10ms
16
AC-Coupled Charge Amplifier
Response of charge amplifier to AC-coupled charge signals
Charge amplifier output: zero-area response
10ms
17
AC-Coupled Charge Amplifier
Response of charge amplifier to AC-coupled charge signals
Charge amplifier output: zero-area response
Negligible dependence on rate: 10kHz and 100kH compared here
10ms
The front-end electronics has to be able to cope with these shifts
18
AC-Coupled Charge Amplifier
Response of charge amplifier to AC-coupled charge signals
Detail
Charge amplifier output: zero-area response
Negligible dependence on rate: 10kHz and 100kH compared here
9.3ms
10ms
The planned decrease in time constant will partly reduce the positive shift
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VMM1/2 Charge Amplifier for Positive Charge
DC source to bias mirror and
recharge input node ~500pA
Ibias
from
sensor
CF
Qin
CF·N
Qout = Qin ·N
-∞
1
to virtual
ground
N
A non-linear asymmetry exists in MOSFET-based integrated front-ends
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AC-Coupled VMM1/2 Front-End
Actual charge amplifier with AC-coupled charge signals
leakage current
adaptive reset
RDET = 10 MΩ
CAC = 470 pF
amplifier
Iout
SHout
CAout
CDET = 100 pF
Charge signals
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Ideal Filter
VMM1 FE
AC-Coupled VMM1/2 Front-End
Response of charge amplifier to AC-coupled charge signals
Voltage amplifier output (CAout)
Charge amplifier current output (Iout)
Shaper output (SHout)
200µs
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AC-Coupled VMM1/2 Front-End
Response of charge amplifier to AC-coupled charge signals
Detail
Voltage amplifier output (CAout)
Charge amplifier current output (Iout): note pole-zero cancellation
Shaper output (SHout)
10µs
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AC-Coupled VMM1/2 Front-End
Response of charge amplifier to AC-coupled charge signals
Voltage amplifier output (CAout)
10kHz, 1pC, leakage 500pA
Charge amplifier current output (Iout)
Shaper output (SHout)
30ms
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AC-Coupled VMM1/2 Front-End
Response of charge amplifier to saturating AC-coupled charge signals
Voltage amplifier output (CAout)
10kHz/1kHz, 1pC/10pC, leakage 500pA
Charge amplifier current output (Iout)
Shaper output (SHout)
30ms
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AC-Coupled VMM1/2 Front-End
Response of charge amplifier to saturating AC-coupled charge signals
Voltage amplifier output (CAout)
10kHz/1kHz, 1pC/10pC, leakage 5nA
Charge amplifier current output (Iout)
Shaper output (SHout)
30ms
An increase in DC leakage current alleviates saturation
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AC-Coupled VMM1/2 Front-End
Response of charge amplifier to AC-coupled charge signals
Voltage amplifier output (CAout)
10kHz/1kHz, 1pC/10pC, leakage 50nA
Charge amplifier current output (Iout)
Shaper output (SHout)
30ms
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The increase in DC leakage current can be high, but it increases the
noise na it may eventually limit the dynamic range
AC-Coupled VMM1/2 Front-End
Response of charge amplifier: higher charge and rate
Voltage amplifier output (CAout)
100kHz/10kHz, 2pC/10pC, leakage 50nA
Charge amplifier current output (Iout)
Shaper output (SHout)
30ms
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AC-Coupled VMM1/2 Front-End
Response of charge amplifier: higher charge and rate
Detail
Voltage amplifier output (CAout)
100kHz/10kHz, 2pC/10pC, leakage 50nA
Charge amplifier current output (Iout)
Shaper output (SHout)
29.3ms
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30ms
Solutions Being Integrated
• Decrease discharge time constant for fast recovery from
saturation and high-rate operation
• Double size of feedback capacitance to reduce voltage swing
• (Implement switchable DC current)
• Modify feedback for dynamic compensating current
1
N
compensating
current
Ibias
from
sensor
CF
Qin
CF·N
Qout = Qin ·N
-∞
1
30
Replica to preserve
pole-zero cancellation
N
to virtual
ground
Note: work in progress
Description of experimental setup and observations made
at the Weizmann Institute on 15 May 2015.
1) Readout of small sTGC prototype strips
2) Readout of Module-1 sTGC pad
31
from Brigitte Vachon and Vladimir Smakhtin, May 2015
1) Readout of small sTGC prototype strips



Small 10x20 cm2 prototype sTGC with strips on both sides.
Chamber operated at nominal operational HV of 2.9kV
Look at signals from Sr-90 radioactive source (rate ~ 10 kHz)
strips
G10
graphite
+HV
wires
graphite
strips
32
from Brigitte Vachon and Vladimir Smakhtin, May 2015
G10
1) Readout of small sTGC prototype strips

Use VMM1 readout


Look at VMM1 analogue pulse
Gain = 0.5 mV/fC, Peak Time = 25 ns, Neighbour channel = off
Use pull-up resistor (20 MΩ) on sTGC adaptor board to inject small
variable current into VMM1.

+2V
20 MΩ
VMM1
Observed change in efficiency as function of current injected into the
VMM1


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Efficiency observed to reach maximum for current of approximately 60 nA.
from Brigitte Vachon and Vladimir Smakhtin, May 2015
1) Readout of small sTGC prototype strips


Recorded raw signals from strips on opposite side of the detector
Raw signals used as input to Gianluigi's simulation
+2V
Raw signal
Channel 4
Strip on
bottom
cathode
50 Ω
20 MΩ
VMM1 analog
output, Channel 2
Strip on
top cathode
Oscilloscope
Agilent, MSO-X 4054A
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from Brigitte Vachon and Vladimir Smakhtin, May 2015
1) Readout of small sTGC prototype strips
Raw strip
signal from
small
10x20 cm2
prototype
VMM1
analogue
output
35
35
from Brigitte Vachon and Vladimir Smakhtin, May 2015
2) Readout of sTGC Module-1 pad

Chamber operated at nominal operational HV of 2.9kV

Look at signals from Sr-90 radioactive source (rate ~ 1-3kHz)

Readout pad with VMM1



Look at VMM1 analogue pulse
Gain = 0.5 mV/fC, Peak Time = 25 ns, Neighbour channel = off
Use pull-up resistor (20 MΩ) on adaptor board to inject small
variable current into VMM1.


36
Observed change in efficiency as function of current injected into
the VMM1 (optimal value observed to be approximately +60nA)
Record VMM1 analogue pad readout using +2 V DC on 20
MΩ pull-up resistor (from ~1V input equals to ~60nA).
from Brigitte Vachon and Vladimir Smakhtin, May 2015
2) Readout of sTGC Module-1 pad
Sr-90 source
VMM1
+2 V DC on
20 MΩ pull-up
resistor
37
from Brigitte Vachon and Vladimir Smakhtin, May 2015
2) Readout of sTGC Module-1 pad
VMM1
analogue
output
38
38
from Brigitte Vachon and Vladimir Smakhtin, May 2015
Note from Vladimir Smakhtin
"During the meeting we have measured signals from strip 10x20 cm2 sTGC.
- after optimization Voffset from 1.2V to 2V value by eye we achieved 100%
efficiency at operation HV=2.9kV and rate per channel ~ 3kHz,
- for this test we are using original method for strip efficiency using two identical
up and down strips
- we have protocol and raw files( full set which needed for modeling and
simulation)
After mini meeting we started tests with Module-1 and pad.
- alignment of Co-60 and optimization of Voffset using scope have been
completed
- developing method for measure rate and efficiency
- we have some very preliminary results
- the results of this activity will be reported in a next meeting"
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Pad capacitance
Taken from: https://indico.cern.ch/event/371991/contribution/1/material/slides/0.pdf
CPH
Example: Area = 164 cm2 (pad 7)
C PP = 0 pF (measured)
C PG = 710 pF (measured)
C PH = (0.15 pF/cm 2)× Apad = 25 pF
ϯϯ C
ϯϯ
PC =
)× A pad = 50 pF
CPW
CPC
+HV
k ϵ0 Apad
∼ 3500 pF
d
k ∼ 4.7
− 12
ϵ 0 = 8.854× 10 F/m
d = 0.1 mm
ϯ Amplifier-Shaper-Discriminator Ics and ASD boards, October 1999 (and re-calculated for sTGC)
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G10
from Brigitte Vachon and Vladimir Smakhtin, May 2015
G10
1.5 mm
ϯC PW = (0.30 pF/cm
2
CPP
CPG
0.2 mm
pad-to-pad
via honeycomb
[Note: Largest pad: Area = 470 cm2]
sTGC cross-section
J. Oliver, “ATLAS Muon New Small Wheel Grounding, Power and Interconnect - Guidelines and Policies”,
https://edms.cern.ch/file/1428856/1/NSW_Grounding_Architecture_v2_20150202_PDR.pdf
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from Brigitte Vachon and Vladimir Smakhtin, May 2015
Additional Discussions 1/2
Average rate as high as 1MHz
Capacitance as high as 2nF
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from Nachman Lupu, May 2015
Additional Discussions 2/2
• Acquisition reset (soft reset)
• Done at falling edge of ENA
• Configuration from SCA (CS,CK,DI,DO)
• SPI in chunks of 96 bits
• Use one of 96 bits to generate global reset (hard reset)
• CS active low (to be confirmed)
• SEU mitigation
• Use DICE or similar for registers
• Use TMR for state machines
• Direct 6-bit output dead time
• Same as high-resolution in simultaneous mode
• Need for L0 buffers and selection logic in VMM
• May be moved off-chip and replaced with double, higher
bandwidth data lines (4 x 320MHz, DDR)
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Fixes (May 2015)
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Issue
Circuit
Solution
Status
Compl
exity
VMM3
Priority
Schema
tics
Layout
TGC saturation: high-charge,
high-rate
Front-end
Fbk time const., fbk capac.,
dynamic current
in prog.
mid
high
in prog.
in prog.
MSB accumulations in 10-bit
and 8-bit ADCs
ADC decision
nodes, PSR
TBD
queued
mid
high
Data repetition
Token/FIFO logic
Token-reset, FIFO alignment
in prog.
mid
high
in prog.
in prog.
High-rate efficiency (discrim.)
Shaping amplifier
Bipolar resp. (SLF bypass)
in prog.
low
high
in prog.
queued
BCID consistency
Gray-code counter
Clock inversion
done
low
high
done
done
Direct timing enable
Control logic
Logic inversion
done
low
high
done
done
Event loss from ADC reset
Channel logic
Logic fix and routing
in rpog.
low
high
done
in prog.
Threshold bit error
Channel logic
Logic fix
done
low
mid
done
done
DAC compression
FET compression
MOSFET size and biasing
done
low
mid
done
done
Pulser rise-time, noise
Injection switch
Size optimization
done
low
mid
done
done
Counter turnaround
Counter cells
Re-routing
done
low
mid
done
done
Front-end disabled in negative
mode with SFM low
Front-end
TBD
queued
low
mid
in prog.
in prog.
High baseline channels
Baseline stabilizer
Increase BLH current
meas.
low
low
queued
Buffer float at bypass
Buffer input stage
Add switch
simul
low
low
done
Decay time in peak detector in
analog readout mode
Leakage hold node
Dual front-end circuit for
voltage and current-mode
simul
mid
low
queued
done
Improvements (May 2015)
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Function
Circuit
Notes
Status
Comple
xity
VMM3
Priority
Schema
tics
Layout
TGC pads 2nF
Front-end
See also recovery from saturation
in prog.
mid
high
in prog.
in prog.
Simultaneous high-res. &
direct-out
Channel and
control logic
Channel reset defined
queued
mid
high
Single-ended config. IOs
Interface
1.2V logic
queued
low
high
Double data-out lines/rate
Interface
4 SLVS diff. output lines, 320 Mb/s DDR
queued
low
mid
SLVS IOs
Digital IOs
Standard 200mV +/- 200mV
in prog.
low
mid
in prog.
queued
Latency reduction in
analog path
Shaping
amplifier
Optional order reduction
queued
mid
mid
Latency reduction in
digital paths
Readout
logic
Concerns latencies for direct and slow
outputs (ck-to-data)
queued
mid
mid
Timing ramp optimization
Analog TAC
Reduce from 125ns to 65ns
done
low
mid
done
done
Configuration interface
Interface
SPI 96-bit w/reset bit
queued
mid
mid
Synchronous ART flag
ART logic
Flag synchronous with ART clock
hold
low
mid
SEU-tolerant logic
Registers &
control
Configuration and state, DICE static +
TRM state
queued
mid
mid
Timeout circuit
Analog TAC
Timeout if no ramp-stop within 1µs
queued
low
low
L0 handling logic
Readout
See Lorne's document
hold
Conclusions
• Saturation in VMM1/2 has been observed with TGC prototypes
• component due to amplitude saturation and long discharge time
constant in charge amplifier - will be addressed with decrease in time
constant, increase in feedback capacitance and, if required, fast recovery
feedback
• component due to shift in charge amplifier output baseline from accoupling - will be addressed with increase in feedback capacitance,
dynamic compensation current and, if required, programmable dc
leakage current
• workaround with injected dc current alleviates saturation, being tested
at Weizmann
• saturation type 2 indicates existence of ac-coupling in detector signal
path
• VMM3 design revision in progress, target July 2015
• we will integrate high and medium-priority items; low-priority items as
time allows
• very limited time to compete the tasks, which increases risks
46
Backup Slides
47
Charge Amplifier Detail
Rs
amplitude ~ Q/CF
charge amplifier
time constant τF from size
of MF and amplitude
Cs
MF
Q
QxN
xN
CF ≈ 2.3 pF
pole-zero cancellation
xN
ENCdisch arg e
(charge gain = N)
1
P
P


kT  CF
 600e 
F
F
2
from non-stationary noise
48
shaper
· simplified schematics
· positive charge circuit