Transcript FE_WA105_March2016x

WA105/ProtoDUNE dual-phase General Meeting
CERN, 7/3/2016
Status of charge readout analog and digital FE
Dario Autiero , L. Balleyguier, E.Bechetoille , D.Caiulo, B.Carlus, L. Chaussard, T.
Dupasquier, S. Galymov , C.Girerd, J. Marteau, H.Mathez, E. Pennacchio, D.Pugnere
IPNL Lyon
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Double-slope ASIC cryogenic amplifiers
16 ch, sdapted to LEM dynamics, like previous version 1200 fC
single slope : larger gain up in the few mip region, kink point point
at 10 mip and reduced gain by a factor 3 up to 40 mips max
dynamic range
 Replace feedback capacitor of the preamplifier with a MOS
capacitance which changes the C value above a certain threshold
voltage (gain ~ 1/C).
Selectable double time constant in discharge or single one with diode
+resistor to keep constant RC
As discussed at the September 2015 CM: we produced a single-slope version in 2013 and a
double-slope version at the end of 2014
 Both versions have noise within specifications and worked correctly at cold and up to 1200
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fC dynamic range.
Double-slope design was improved and new circuit submitted in September and received at the
beginning of January:
- Design of MOSCAP less process dependent
- Removal of parasitic capacitance on feedback resistor branch
- Better differential driver integrated from another IN2P3 development
~log regime up to 1200 fC
Kink at 400 fC
~13 mip with
LEM gain = 20
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New circuit (LARZIC_2015)produced as a test batch (25 units) with purchase option for already
produced 600 units (entire WA105 production for 6x6x6 ) if the tests on the 25 ordered units
were satisfactory and confirming expectations
 ASIC tested at warm and cold
at the beginning of January, test
successful and complying to
expectations from the circuit
specifications.
ENC as a function of input capacitance
and for various temperatures at the
output of the preamplifier +differential
driver
Effect of shaper, mounted on ADC card,
not included:
ENC (before shaping) at 110 K=
3.18*C+442=1396 e- at 300 fC
Similar figure to previous version before
shaping (after shaping better figure
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previous version~1200 e-)
Accessible cold front-end electronics and uTCA DAQ system
Full accessibility provided by the double-phase charge readout at the top of the detector
 Digital electronics at warm on the tank deck:  Cryogenic ASIC amplifiers (CMOS 0.35um)
16ch externally accessible:
• Architecture based on uTCA standard
• 1 crate/signal chimney, 640 channels/crate
• Working at 110K at the bottom of the signal
 12 uTCA crates, 10 AMC cards/crate, 64 ch/card
chimneys
• Cards fixed to a plug accessible from outside
Short cables capacitance, low noise at low T
Warm
ASICs 16 ch.
(CMOS 0.35 um)
uTCA crate
Cold
CRP
Signal chimney
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Isolation
transformer
General grounding scheme:
Multiplug 230 V
Isolation
transformer
Slow
control
Neutral grounded to cryostat ?
The cryostat metallic
structure defines the
common ground via a star
topology connections
LV PS
GND
GND
LV shielded cable
Patch box or
flange PCB
Chimney +
warm
flange
uTCA
GND
ADC connections
SC connections
The electrical equipments are
connected to the 230V AC via
isolation transformers
Cryostat
Noise decoupling among
different AC equipments is
obtained by putting another
isolation transformer in
series to the most sensitive
equipments
Cryostat GND
Preamps
Example of main
isolation
transformer
provided by Francois
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FE cards and warm flange connections:
Warm
flange
PCB
Warm flange actual design: x5(80 pins and 68 pins KEL
connectors) = 148 lines
Cold FE card: 40 and 34 pairs KEL connectors
FE cards: integrating 4 ASICs, connectors, protection
diodes + some blocking capacitors
40 pairs
34 pairs
64 channels/card  4 ASICS of 16 channels/card
Flat cables occupancy:
 2x32 pairs for signals = 128 connections
 5 LV connections for 3.3,2.4,2.1,Vref,GND
 5 lines for calibrations and controls:
- feedback diode enable
-general enable on/off (related to power switching
-calibration:
a) pulse
b) clock and c) data (daisy chain to select individually
the channels) SPI
5+128+5= 138 lines  10 spare lines (to be used for
better grounding/LV connections)
Warm
Fake FE card for mechanical tests
Cold
 FE card being finalized after ASIC validation
 Assignment of lines and routing to warm flange
connectors with separate functions (LV, SC, ADC)
RC discharge
Double opposite diodes components preferred for capacitance and
performance
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1st
option
Typical capacitance at 1MHz is 1pF
Peak pulse power (bidirectional) 250W
Peak pulse current rating: 15A
http://fr.farnell.com/bourns/cdsod323t08lc/diode-tvs-bi-8v-1pf-sod323/dp/2341923
Note: tested with max LEM voltage of 3.4
kV. Accumulated 23 LEM discharges  no
damage to op-amp in current monitoring
circuit observed
Capacitance < 1 pF
Peak pulse power 200W
Peak pulse current rating: 5A
http://fr.farnell.com/semtech/rclamp1502b/
diode-tvs-dual-esd-high-s-sc75/dp/2058985?ost=2058985
uTCA charge readout architecture
uTCA crates

640 channels/chimney

1 uTCA crate/chimney, 10 Gb/s link

10 AMC digitization boards per uTCA crate, 64 readout channels per AMC board, memory buffer
12228 samples/channel
 12
Readout in groups of 640 channels/chimney
uTCA crates for charge readout + 1 uTCA crate for light readout
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11
DAQ timing-trigger integration
Time
WR Clock + time + triggers
WR slave MCH mezzanine
CC 1
Meinberg GPS
CC 6
CC 2
White Rabbit
GrandMaster
switch
CC 12
CC 7
PMC
Light
readout
Charge readout
Digitized data
Data processing PC 1
6 10 GbE links + 2 spares
Data processing PC 2
Trigger PC
7 10 GbE links + 1 spares
WR slave
trigger
board
Bittware card 1
WR Clock +
time + triggers
Bittware card 2
Time
Beam window
NIM signal every 20 s
Cosmics counters
Beam Trigger counter
NIM signal ~ a few 12
100 Hz
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Data acquisition demonstrator
(available since January 2015)
•
•
•
•
Based on µTCA AMC S4AM from Bittware
FMC mezzanine board with 64 ADC channels
Control through GbE
Data transmission through 10GbE
Prototype of the 64 channels AMC digitization
card (2.5-25 MHz, 12 bits, 2V, AD5297) hosted on
Bittware S4AM, 10 GbE output on uTCA backplane
AMC
S4AM
64 ADC ch
FMC
mezzanine
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Final card synoptics including clock distribution
 uTCA cards production started in November 2015, on the 2015 budget, with the
purchase of all the main components needed for the entire 6x6x6 production defined in
the AMC design: FPGA (Cyclone V GX, 120 pieces), Dual port memory (IDT70V3339, 240
pieces) , ADCs (AD9257BCPZ-40, 8/card, 1040 pieces) for ~100 keur (2016 budget is
being attributed at the moment)
 The full components for the first 10 cards were also purchased and the tenders for their
production (PCB, assembly) launched (2 PCBs immediately assembled for tests + 8 PCBs
held upon validation of the first two)
 Production of the first 10 cards was delayed due to the availability of some components
and the routing of the card which is quite complex (14 layers) and assigned to a common
service at IPNL independent on the developers in our group and also serving other
projects.
 The routing of the card is now being finalized and we should get the 10 cards in May in
order to start using them on the 3x1x1
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Conclusions:
 The production of the FE for the 6x6x6 started at the end of 2015 with the available funding of that year
both for the analog and digital electronics and with the goal of already using this electronics on the
3x1x1
 ASIC Double-slope version resubmitted in September with some corrections has been validated . The 25
chips batch tested in January provides satisfactory results in line with expectations. Massive production
of 600 chips for the 6x6x6 (up to 25% spares) was performed at the same time as the test batch of 25
circuits with purchase option of the entire sample on the 2016 budget in case of satisfactory results.
This purchase option is now confirmed.

Completing the FE cards hosting the ASICs + purely passive components + general integration and
grounding
 Design phase of AMC digitization cards completed on the basis of S4AM prototype, components frozen.
Massive purchase of most expensive components launched in November 2015. Routing of the circuit
delayed with respect to initial planning due to availability of the service and now being completed. Prebatch of 10 cards to be first deployed on 3x1x1 should be available in May. Then full assembly of
remaining 100 cards will be launched.
 3x1x1 DAQ system nicely complemented by a smaller scale test version of the online storage/computing
farm (see Jacques talk). Funding requested by ETH in October now available. Progress on tests for the
design of the system. Implementation helped by people from IT division.
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