Networking for Embedded Systems
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Transcript Networking for Embedded Systems
The Embedded computing
platform
CPU bus.
Memory.
I/O devices.
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CPU bus
Connects CPU to:
memory;
devices.
Protocol controls communication between
entities.
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Bus protocol
Determines who gets to use the bus at
any particular time.
Governs length, style of communication.
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Four-cycle handshake
Basis of many bus protocols.
Uses two wires:
enq (enquiry);
ack (acknowledgment).
enq
dev1
data
dev2
ack
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Four-cycle example
enq
1
3
2
data
4
ack
time
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Typical bus signals
Clock.
R/W’: true when bus is reading.
Address: a-bit bundle.
Data: n-bit bundle.
Data ready’.
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Timing diagrams
one
A
rising
10 ns
zero
falling
stable
B
changing
C
time
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Typical bus timing for read
CPU:
set R/W’=1;
asserts address, address enable.
Memory:
asserts data;
asserts data ready’.
CPU:
deasserts address, address enable.
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Bus read state diagram
Get
data
Done
See ack
Adrs
Wait
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Transaction types
Wait state:
state in a bus transaction to wait for
acknowledgment.
Disconnected transfer:
bus is freed during wait state.
Burst:
multiple transfers.
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Timers and counters
Very similar:
a timer is incremented by a periodic signal;
a counter is incremented by an
asynchronous, occasional signal.
Rollover causes interrupt.
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Watchdog timer
Watchdog timer is periodically reset by
system timer.
If watchdog is not reset, it generates an
interrupt to reset the host.
interrupt
host CPU
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reset
watchdog
timer
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Switch debouncing
A switch must be debounced to multiple
contacts caused by eliminate mechanical
bouncing:
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Encoded keyboard
An array of switches is read by an
encoder.
N-key rollover remembers multiple key
depressions.
row
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LED
Must use resistor to limit current:
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7-segment LCD display
May use parallel or multiplexed input.
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Types of high-resolution
display
Cathode ray tube (CRT)
Liquid crystal display (LCD)
Plasma, etc.
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Touchscreen
Includes input and output device.
Input device is a two-dimensional
voltmeter:
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Touchscreen position
sensing
ADC
voltage
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Digital-to-analog
conversion
Use resistor tree:
R
bn
bn-1
bn-2
Vout
2R
4R
8R
bn-3
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Flash A/D conversion
N-bit result requires 2n comparators:
Vin
encoder
...
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Dual-slope conversion
Use counter to time required to
charge/discharge capacitor.
Charging, then discharging eliminates
non-linearities.
Vin
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timer
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Sample-and-hold
Required in any A/D:
Vin
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converter
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