Transcript Field Effect Transistor

ECA1212
Introduction to Electrical &
Electronics Engineering
Chapter 6: Field Effect Transistor
by Muhazam Mustapha, October 2011
Learning Outcome
By the end of this chapter students are
expected to:
• Be able to explain some basic physical
theory and operation of FET
• Be able to do calculation on DC and AC
analysis on FET circuit
Chapter Content
• Theory of FET
• FET Operation
• FET in Digital Circuit
Field Effect Transistor
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Field Effect Transistor
• FET is a piece of electronic device that
conducts electricity by the control of a gate
• It can be considered as a voltage controlled
resistor or voltage controlled current source
• Current flows through the
center body of channel
from terminals called drain
to source
• Gate is a plate not
touching the substrate
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Drain
Gate
Channel
Source
FET Types
• There are many types of FET
– MOSFET – Metal Oxide Semiconductor FET
– JFET – Junction FET
– NMOS – n-channel MOSFET
– PMOS – p-channel MOSFET
• We will cover mostly NMOS
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Channel Types
• FET is also characterized by its channel
• n-channel
– The majority carrier in the channel is electron
• p-channel
– The majority carrier in the channel is hole
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Modes
• Enhancement mode
– FET is normally NOT conducting current even
when given voltage at drain and source
– Gate is to increase the current
• Depletion mode
– FET is normally conducting current when
given voltage at drain and source
– Gate is to decrease the current
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Depletion Mode
• p-channel
Drain
+ve
– Current flow is reduced by
putting a positive voltage at
gate to repel holes flow and
finally block the current
– The more positive the gate,
the less current flow
Gate
+ve
Gate’s electric
field repelling
holes
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Hole
Flow
p-channel
−ve
Source
Depletion Mode
• n-channel
– Current flow is reduced by
putting a negative voltage
at gate to repel electrons
flow and finally block the
current
– The more negative the
gate, the less current flow
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Drain
+ve
Gate
Electron
Flow
−ve
n-channel
Gate’s electric
field repelling
electrons
−ve
Source
Enhancement Mode (PMOS)
n-substrate
• p-channel
– When negative voltage is put
to drain that is made of highly
p dopant (p+), reverse bias
junction is formed at drain –
hence no current flows
– Negative voltage is put to
gate to attract holes and
effectively compensate the
reverse biases – until current
can flow
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p-channel
formation
Drain
−ve
p+
Gate
−ve
Hole
Flow
p+
Gate’s electric
field attracting
holes
+ve
Source
Enhancement Mode (NMOS)
p-substrate
• n-channel
– When positive voltage is put
to drain that is made of highly
n dopant (n+), reverse bias
junction is formed at drain –
hence no current flows
– Positive voltage is put to gate
to attract electrons and
effectively compensate the
reverse biases – until current
can flow
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n-channel
formation
Drain
+ve
n+
Gate
+ve
Electron
Flow
n+
Gate’s electric
field attracting
electrons
−ve
Source
Circuit Symbol and Notations
Depletion
p-channel
n-channel
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Enhancement
JFET
Operation Region
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I-V Characteristic
ID, mA
VGS = 5.0V
Ohmic
Region
15
VGS = 4.5V
Saturation
Region
10
VGS = 4.0V
VGS = 3.5V
5
VGS = 3.0V
VGS = 2.5V
0
0
1
2
3
4
5
Cutoff
Region
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6
7
8
9
VDS, V
Operation Region
• Cutoff
– VGS < VT and VGD < VT
– No current flow
• Ohmic / Triode
– VGS > VT and VGD > VT
– Linear I-V characteristic
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Operation Region
• Saturation
– VGS > VT and VGD < VT
– ID is controlled by VGS (Saturation Region
Formula):
I D  K (VGS  VT )
Conductance
parameter
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2
Threshold voltage –
minimum voltage to form a
conducting channel
FET In Digital Circuit
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NAND, NOR and NOT Gates
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