Chapter4 DC Biasing BJT (part a)
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Transcript Chapter4 DC Biasing BJT (part a)
DMT 121 – ELECTRONIC 1
Chapter 4
DC Biasing – Bipolar Junction Transistors (BJTs)
OBJECTIVES
Discuss the concept of dc biasing of a transistor
Analyze voltage-divider bias, base bias, emitter bias and
collector-feedback bias circuits.
Basic troubleshooting for transistor bias circuits.
INTRODUCTION
For the transistor to properly operate it must be biased.
There are several methods to establish the DC operating
point.
We will discuss some of the methods used for biasing
transistors as well as troubleshooting methods used for
transistor bias circuits.
BIASING & 3 STATES OF OPERATION
Active or Linear Region Operation
Base–Emitter junction is forward biased
Base–Collector junction is reverse biased
Cutoff Region Operation
Base–Emitter junction is reverse biased
Saturation Region Operation
Base–Emitter junction is forward biased
Base–Collector junction is forward biased
DC OPERATING POINT
The goal of amplification in most cases is to increase the
amplitude of an ac signal without altering it.
DC OPERATING POINT
For a transistor circuit to amplify it must be properly biased with dc
voltages. The dc operating point between saturation and cutoff is
called the Q-point. The goal is to set the Q-point such that that it
does not go into saturation or cutoff when an a ac signal is applied.
IB IC and VCE
IB IC and VCE
DC OPERATING POINT
Recall that the collector characteristic curves graphically show the
relationship of collector current and VCE for different base
currents. With the dc load line superimposed across the collector
curves for this particular transistor we see that 30 mA (IB = 300
A) of collector current is best for maximum amplification, giving
equal amount above and below the Q-point. Note that this is
three different scenarios of collector current being viewed
simultaneously.
DC OPERATING POINT
With a good Q-point established, look at the effect of superimposed ac
voltage has on the circuit. Note the collector current swings do not
exceed the limits of operation (saturation and cutoff). However, as
you might already know, applying too much ac voltage to the base would
result in driving the collector current into saturation or cutoff resulting in a
distorted or clipped waveform.
Key terms
DC Load Line
A straight line plot of IC and VCE for a transistor circuit.
Q-point
DC operating point along line between saturation and
cutoff
Linear Region
A region of operation along the load line between
saturation and cutoff
WAVEFORM DISTORTION
Graphical load line illustration of a transistor being driven into
saturation and/or cutoff
WAVEFORM DISTORTION
FIXED-BIAS (BASE-BIAS) CIRCUIT
Simplest transistor bias configuration.
Commonly used in relay driver circuits.
Extremely beta-dependant and very unstable
Fixed-bias circuit.
DC equivalent circuit.
FIXED-BIAS (BASE-BIAS) CIRCUIT
Base – Emitter loop
VCC IBRB VBE 0
VCC VBE
IB
RB
VBE = VB – VE (since VE = 0)
VBE = VB
Collector – Emitter loop
Measuring VCE and VC.
VCC – ICRC – VCE = 0
VCC VCE
VCE = VCC – ICRC; then IC
RC
= VC – VE since VE = 0
VCE = VC
Since IC = IB, then
Sensitive to Beta
VCC VBE
IC
RB
Fixed-bias (base-bias) - Summary
Circuit recognition :
A single resistor (RB) between the base terminal
and VCC. No emitter resistor.
Q-point stability :
Q-point is more dependent on βdc, so it becomes β
dependent and unpredictable.
Βdc varies with temperature and IC.
Advantage: Circuit simplicity.
Disadvantage: Q-point shift with temperature
Applications: Switching circuits only. Rarely used in
linear operation.
Cont’d Summary
Load line equations:
I C (sat )
VCC
RC
VCE (off ) VCC
Q-point equations:
IB
VCC VBE
RB
VCC VBE
IC
RB
VCE VCC ICRC
EXAMPLE
Given that VBE = 0.7 V and βDC = 100, determine the Q-point values
EXAMPLE
Given that VBE = 0.7 V, RB=22kΩ, RC=100 Ω and βDC =
90, determine the Q-point values
EMITER BIAS
Use both a positive and a negative supply voltage on emitter or
it just contain an emitter resistor to improve stability level over
fixed – bias configuration.
BJT bias circuit with emitter resistor.
An npn transistor with emitter bias.
Polarities are reversed for a pnp transistor.
Single subscripts indicate voltages with
respect to ground.
EMITER BIAS – only RE
Collector – Emitter loop
VCC – ICRC – VCE – IERE = 0
IE IC
VCC – ICRC – VCE –ICRE = 0
VCC – VCE = IC (RC + RE)
BJT bias circuit with emitter
resistor.
Base – Emitter loop
VCC – IBRB – VBE – IERE = 0
IE = ( + 1) IB
Then, VCC – IBRB – VBE – ( + 1)IBRE = 0.
VCC VBE
IB
RB ( 1) RE
VCC VCE
IC
RC RE
Since IC = IB, so IC also equivalent to
(VCC VBE)
IC
RB ( 1) RE
Less sensitivity to beta
EMITER BIAS –RE + DC Voltage Supply
Collector – Emitter loop
VCC – ICRC – VCE – IERE + VEE = 0
IE IC
VCC – ICRC – VCE –ICRE + VEE = 0
VCC – VCE + VEE = IC (RC + RE)
VCC VCE VEE
IC
RC RE
Base – Emitter loop
VEE + IBRB + VBE + IERE = 0
IE = ( + 1) IB
Then, VEE + IBRB + VBE + ( + 1)IBRE = 0.
VEE VBE
IB
RB ( 1) RE
(VEE VBE )
IC
RB ( 1) RE
Less sensitivity to beta
EMITTER BIAS - Summary
Circuit recognition:
Dual-polarity power supply (+ve and -ve) and the base resistor is
connected to ground.
Stability :
Adding RE to the emitter improves the stability of a transistor
Stability refers to a bias circuit in which the currents and voltages
will remain fairly constant for a wide range of temperatures and
transistor Beta () values.
Advantage: The circuit Q-point values are stable against changes in β.
Disadvantage: Requires the use of dual-polarity power supply.
Applications: Used primarily to bias linear amplifiers.
EMITTER BIAS - Summary
With DC Voltage supply +
Resistor at Emitter
BE LOOP
IB
IC
(VEE VBE )
RB ( 1) RE
BE LOOP
CE LOOP
VEE VBE
VCC VCE VEE
IC
RB ( 1) RE
RC RE
Since IC = βIB , so
With only Resistor at Emitter
IB
VCC VCE
VCC VBE
IC
RC RE
RB ( 1) RE
Since IC = βIB , so
IC
CE LOOP
(VCC VBE)
RB ( 1) RE
EMITTER BIAS - Summary
Previous analysis we use IE = ( + 1) IB; but if use IE IC IB, then
from previous slide we can get.
IC
VEE VBE
RB
RE
OR we also can use ( + 1) to get the same result.
•If RE >>> RB/ then we can drop RB/ in equation
VEE VBE
IC
RE
Less sensitivity to beta
or independent to beta
•If VEE >>> VBE then
VEE
IC
RE
Independent to VBE
EMITTER BIAS - Summary
Load line equations:
I C (sat )
VCC (VEE ) VCC VEE
RC RE
RC RE
VCE (off ) VCC VEE VCC VEE
Q-point equations:
VEE VCC
IB
RB ( 1) RE
VEE VCC
IC
RB ( 1) RE
VCE VCC IC ( RC RE ) VEE
EMITTER BIAS - Summary
Voltage with respect to ground :
Emitter voltage;
VE = VEE+IERE
Base voltage;
VB = VE + VBE
Collector voltage;
VC = VCC - ICRC
EXAMPLE
Given that Vcc = +12V,VEE = -12V, RB=100kΩ, RC=750 Ω, RE
=1.5kΩ, β=200. Find the value of IB,IE and VCE
EXAMPLE
Given that Vcc = 5V,VEE = -5V, RB=10kΩ, RC=1.0k Ω, RE =2.2kΩ,
β=100. Find the voltage of terminal with respect to ground
EXAMPLE
From previous Figure, Find the voltage of terminal with
respect to ground