Transcript cpe323msp430_reset_clocks

CPE 323 Introduction to
Embedded Computer Systems:
The MSP430 System Architecture
Instructor: Dr Aleksandar Milenkovic
Lecture Notes
Outline
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MSP430: System Architecture
System Resets, Interrupts, and
Operating Modes
Basic Clock Module
Watchdog Timer
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MSP430: System Resets, Interrupts, and
Operating Modes
Resets
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Reset – a sequence of operations that put device
into a well-defined state (from which the user’s
program may start)
Performed when
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Power is first applied and
Device detects serious fault in hardware or software from
which the user’s program cannot be expected to recover
MSP430 supports two types of reset (HW and SW
controlled)
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Power-on Reset (POR)
Power-up Clear (PUC)
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Power-on Reset (POR)
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Generated by the following severe conditions related
to hardware
Device is powered-up. POR us raised if the supply
voltage drops to so low a value that the device may
not work correctly. Include brownout detector.
A low external signal on the #RST/NMI pin (if the pin
is configured for the reset function rather than the
nonmaskable interrupt). Active by default
Some MSP430s have a more comprehensive supply
voltage supervisor (SVS). It sets the SVSFG flag if the
voltage falls below the programmed level and can
optionally reset the device
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Power-Up Clear (PUC)
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It always follows the POR. It is generated when software
appears to be out of control
Watchdog time overflows in watchdog mode
Write into the watchdog control register (WDTCTL) with
incorrect password in the upper byte. Can be triggered even
if the WDT is disabled or operates in the interval mode
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Write an incorrect password into the flash memory controller
registers (FCTLn)
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Correct password is 0x5A available as symbol WDTPW
Protects the stored program from a runaway software
In newer devices, a PUC is triggered when we try to fetch an
instruction from the range of addresses reserved for
peripheral I/O or for unimplemented memory
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System Reset
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Power-on Reset (POR)
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Powering up the device
A low signal on the RST/NMI pin when
configured in the reset mode
An SVS low condition when PORON=1.
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Power-up Clear
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A POR signal
Watchdog timer expiration when in
watchdog mode only
Watchdog timer security key violation
A Flash memory security key violation
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Power-On Reset (POR)
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Brownout Reset
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Conditions after Reset
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Initial conditions for all registers and peripherals
after POR and PUC are specified in the family’s user
guides; some common effects
#RST/NMI pin is configured for reset
Most I/O pins are configured as digital inputs
For registers see the manual. Notation is as follows
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rw-0: means that a bit can be read and written and is
initialized to 0 after a PUC
rw-(0): means that a bit can be read and written and is
initialized to 0 after a POR and retains its value after a PUC
Status register is cleared (R2=0): active mode
WDT starts in watchdog mode
PC is loaded with the reset vector which is @0xFFFE
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Reset related flags
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How to identify a source of the reset when
debugging
IFG – Interrupt Flag Register (IFG1, IFG2)
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WDTIFG: shows that the WDT timed out or its security key
is violated
OFIFG: indicates an oscillator fault (causes a nonmaskable
interrupt, not reset)
RSTIFG: indicates a reset caused by a signal on the
#RST/NMI pin
PORIFG: is set on power-on reset
NMIIFG: flags a non-maskable interrupt caused by a signal
on #RST/NMI
These bits are not cleared by a PUC, so they can be
tested to identify the source of the PUC
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Software configuration
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Your SW must configure the MSP430
Initialize the SP, typically to the top of RAM
Configure the watchdog to
the requirements of the application
Setup the clock (clocks)
Configure all ports (unused pins should never be left as
floating inputs).
Configure peripheral modules to the requirements of the
application (e.g. TimerA, ADC12, ...)
Finally enable interrupts if needed
Note: Additionally, the watchdog timer, oscillator fault, and
flash memory flags can be evaluated to determine the source
of the reset
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Interrupts
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3 types
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System reset
(Non)-maskable
NMI
Maskable
Interrupt
priorities are fixed
and defined by
the arrangement
of modules
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(Non)-Maskable Interrupts (NMI)
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Sources
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An edge on the RST/NMI pin
when configured in NMI mode
An oscillator fault occurs
An access violation to the flash memory
Are not masked by GIE (General Interrupt Enable),
but are enabled by individual interrupt enable bits
(NMIIE, OFIE, ACCVIE)
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NMI Interrupt Handler
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Maskable Interrupts
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Caused by peripherals with interrupt capability
Each can be disabled individually by
an interrupt enable bit
All can be disabled by GIE bit in the status register
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Interrupt acceptance
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1) Any currently executing instruction is completed.
2) The PC, which points to the next instruction, is pushed onto the stack.
3) The SR is pushed onto the stack.
4) The interrupt with the highest priority is selected if multiple interrupts
occurred during the last instruction and are pending for service.
5) The interrupt request flag resets automatically on single-source flags.
Multiple source flags remain set for servicing by software.
6) The SR is cleared with the exception of SCG0, which is left unchanged.
This terminates any low-power mode. Because the GIE bit is cleared,
further interrupts are disabled.
7) The content of the interrupt vector is loaded into the PC: the program
continues with the interrupt service routine at that address.
Takes 6 cc to execute
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Return from Interrupt
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RETI - Return from Interrupt Service Routine
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1) The SR with all previous settings pops from the stack.
All previous settings of GIE, CPUOFF, etc. are now in effect,
regardless of the settings used during the interrupt service
routine.
2) The PC pops from the stack and begins execution at the
point where it was interrupted.
Takes 5 cc to execute
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Interrupt Vectors
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Interrupt Service Routines
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Interrupt Service Routine declaration
// Func. declaration
Interrupt[int_vector] void myISR (Void);
Interrupt[int_vector] void myISR (Void)
{
// ISR code
}
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EXAMPLE
Interrupt[TIMERA0_VECTOR] void myISR (Void);
Interrupt[TIMERA0_VECTOR] void myISR (Void)
{
// ISR code
}
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Interrupt Vectors
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
PORT2_VECTOR
UART1TX_VECTOR
UART1RX_VECTOR
PORT1_VECTOR
TIMERA1_VECTOR
TIMERA0_VECTOR
ADC_VECTOR
UART0TX_VECTOR
UART0RX_VECTOR
WDT_VECTOR
COMPARATORA_VECTOR
TIMERB1_VECTOR
TIMERB0_VECTOR
NMI_VECTOR
RESET_VECTOR
1 * 2
2 * 2
3 * 2
4 * 2
5 * 2
6 * 2
7 * 2
8 * 2
9 * 2
10 * 2
11 * 2
12 * 2
13 * 2
14 * 2
15 * 2
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
0xFFE2
0xFFE4
0xFFE6
0xFFE8
0xFFEA
0xFFEC
0xFFEE
0xFFF0
0xFFF2
0xFFF4
0xFFF6
0xFFF8
0xFFFA
0xFFFC
0xFFFE
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Port 2 */
UART 1 Transmit */
UART 1 Receive */
Port 1 */
Timer A CC1-2, TA */
Timer A CC0 */
ADC */
UART 0 Transmit */
UART 0 Receive */
Watchdog Timer */
Comparator A */
Timer B 1-7 */
Timer B 0 */
Non-maskable */
Reset [Highest Pr.] */
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Operating Modes
(to be discussed later)
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MSP430: Clock System
Clock System: An Introduction
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Clock – square wave whose edges trigger hardware
Traditional clocks: a crystal with frequency of a few
MHz is connected to two C pins; internally the
clock may be divided by 2 or 4.
Typical application cycle in embedded systems
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C stays in a low-power mode until
An event wakes up C to handle it
Often need multiple clocks
(fast for CPU, slow for peripherals)
Power consumption: P ~ CV2f
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Clock System: An Introduction
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Crystal clocks
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Accurate (the frequency is typically within 11 part in
100,000), stable (do not change with time or temperature)
High-frequency (a few MHz) or low-frequency (32,768 Hz)
for a real-time clock
Expensive, delicate, draw a relatively large current, require
additional components (capacitors), take long time to start
up and stabilize
Resistor and capacitor (RC) clocks
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Cheap, quick to start
Poor accuracy and stability
Can be external or integrated into a chip
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MS430 Clock System
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Flexible to address conflicting demands for highperformance, low-power, and a precise frequency
3 internal clocks from 4 possible sources: MCLK,
SMCLK, ACLK
Master clock, MCLK: used by the CPU and a few
peripherals (e.g., ADC12, DMA, ...)
Subsystem master clock, SMCLK:
distributed to peripherals
Auxiliary clock, ACLK: distributed to peripherals
Typical configuration: MCLK and SMCLK are in the
megahertz range, ACLK is 32 KHz
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Clock System: MSP430
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Digitally controlled Oscillator, DCO:
available in all devices; highlycontrollable oscillator
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Low- or high-frequency crystal
oscillator, LFXT1
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Generated on-chip RC-type
frequency controlled by SW + HW
LF: 32768Hz
XT: 450kHz .... 8MHz
High-frequency crystal oscillator, XT2
Internal very low-power, lowfrequency oscillator, VLO: available in
more recent MSP430F2xx devices;
provides an alternative to LFXT1
when accuracy is not needed
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Basic Clock System: MSP430x1xx
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DCOCLK Generated on-chip with 6s start-up
32KHz Watch Crystal - or - High Speed Crystal / Resonator to 8MHz
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(our system is 4MHz/8MHz high Speed Crystal)
Flexible clock distribution tree for CPU and peripherals
Programmable open-loop DCO Clock with
internal and external current source
LFXT1 oscillator
32kHz
XIN
LFXT1CLK
ACLK
Auxiliary Clock
to peripherals
8MHz
XOUT
LFXT2CLK
Clock
Distribution
100kHz - 5MHZ
Rosc
Digital Controlled Oscillator DCOCLK
DCO
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MCLK
Main System Clock
to CPU
SMCLK
Sub-System Clock
to peripherals
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Basic Clock System – Block Diagram
DIVA
2
LFXTCLK
/1, /2, /4, /8
OscOff
XTS
ACLKGEN
ACLK
Auxiliary Clock
SELM DIVM CPUOff
High frequency
2
XT oscillator, XTS=1
Vcc
2
DCO
MOD
3
0
P2.5
/Rosc
0,1
Low power
Vcc LF oscillator, XTS=0
Rsel SCG0
1
DCOR
DCGenerator
DCGEN
2
3
5
/1, /2, /4, /8, off
MCLK
MCLKGEN
Main System Clock
SELS DIVS SCG1
DCOCLK
2
Digital Controlled Oscillator DCO
0
Modulator MOD
1
DCOMOD
SMCLK
/1, /2, /4, /8, off
+
SMCLKGEN
Sub-System Clock
The DCO-Generator is connected to pin P2.5/Rosc if DCOR control bit is set.
The port pin P2.5/Rosc is selected if DCOR control bit is reset (initial state).
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Basic clock block diagram
(MSP430x13x/14x/15x/16x)
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Basic operation
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After POC (Power Up Clear)
MCLK and SMCLK are sourced by DCOCLK (approx. 800KHz) and ACLK is
sourced by LFXT1 in LF mode
Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure
the MSP430 operating modes and enable or disable portions of the basic
clock module
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SCG1 - when set, turns off the SMCLK
SCG0 - when set, turns off the DCO dc generator
(if DCOCLK is not used for MCLK or SMCLK)
OSCOFF - when set, turns off the LFXT1 crystal oscillator
(if LFXT1CLK is not use for MCLK or SMCLK)
CPUOFF - when set, turns off the CPU
DCOCTL, BCSCTL1, and BCSCTL2 registers
configure the basic clock module
The basic clock can be configured or reconfigured by software at any time
during program execution
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Basic Clock Module - Control Registers
The Basic Clock Module is configured using control registers DCOCTL, BCSCTL1, and
BCSCTL2, and four bits from the CPU status register: SCG1, SCG0, OscOff, and CPUOFF.
User software can modify these control registers from their default condition at any time. The
Basic Clock Module control registers are located in the byte-wide peripheral map and should
be accessed with byte (.B) instructions.
Register State
DCO control
register
Basic clock
system control 1
Basic clock
system control 2
Short Form
Register Type
Address
DCOCTL
Read/write
056h
060h
BCSCTL1
Read/write
057h
084h
BCSCTL2
Read/write
058h
reset
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Initial State
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Basic Clock Module - Control Registers
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BCSCTL2
Direct SW Control
DCOCLK can be Set - Stabilized
Stable DCOCLK over Temp/Vcc.
058h
SELM.1 SELM.0 DIVM.1 DIVM.0 SELS
rw-0
rw-0
BCSCTL1
DCOCTL
057h
056h
XT2Off XTS DIVA.1 DIVA.0 XT5V
rw-(1)
rw-(0)
rw-(0)
rw-(0)
rw-0
Rsel.2 Rsel.1 Rsel.0
rw-1
rw-0
rw-0
Selection of
DCO nominal
frequency
rw-0
rw-0
rw-0
DIVS.1 DIVS.0 DCOR
rw-0
rw-0
rw-0
DCO.2 DCO.1 DCO.0 MOD.4 MOD.3 MOD.2 MOD.1 MOD.0
rw-0
rw-1
rw-1
rw-0
Which of eight
discrete DCO
frequencies is
selected
rw-0
rw-0
rw-0
rw-0
Define how often frequency
fDCO+1 within the period of
32 DCOCLK cycles is
used. Remaining clock
cycles (32-MOD) the
frequency fDCO is mixed
RSEL.x Select DCO nominal frequency
DCO.x and MOD.x set exact DCOCLK
… select other clock tree options
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DCOCTL
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Digitally-Controlled Oscillator (DCO) Clock-Frequency Control
DCOCTL is loaded with a value of 060h with a valid PUC condition.
7
0
DCOCTL DCO.2 DCO.1 DCO.0 MOD.4 MOD.3 MOD.2 MOD.1 MOD.0
056H
0
1
1
0
0
0
0
0
MOD.0 .. MOD.4: The MOD constant defines how often the discrete frequency fDCO+1 is
used within a period of 32 DCOCLK cycles.
During the remaining clock cycles (32–MOD) the discrete frequency f DCO is used. When
the DCO constant is set to seven, no modulation is possible since the highest feasible
frequency has then been selected.
DCO.0 .. DCO.2: The DCO constant defines which one of the eight discrete frequencies is
selected. The frequency is defined by the current injected into the dc generator.
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BCSCTL1

Oscillator and Clock Control Register
BCSCTL1 is affected by a valid PUC or POR condition.
7
0
BCSCTL1 XT2Off XTS DIVA.1 DIVA.0 XT5V Rsel.2 Rsel.1 Rsel.0
057h
1
0
0
0
0
1
0
0
Bit0 to Bit2: The internal resistor is selected in eight different steps.
Rsel.0 to Rsel.2 The value of the resistor defines the nominal frequency.
The lowest nominal frequency is selected by setting Rsel=0.
Bit3, XT5V: XT5V should always be reset.
Bit4 to Bit5: The selected source for ACLK is divided by:
DIVA = 0: 1
DIVA = 1: 2
DIVA = 2: 4
DIVA = 3: 8
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BCSCTL1
Bit6, XTS: The LFXT1 oscillator operates with a low-frequency or with a highfrequency crystal:
XTS = 0: The low-frequency oscillator is selected.
XTS = 1: The high-frequency oscillator is selected.
The oscillator selection must meet the external crystal’s operating condition.
Bit7, XT2Off: The XT2 oscillator is switched on or off:
XT2Off = 0: the oscillator is on
XT2Off = 1: the oscillator is off if it is not used for MCLK or SMCLK.
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BCSCTL2
BCSCTL2 is affected by a valid PUC or POR condition.
7
0
BCSCTL2 SELM.1 SELM.0 DIVM.1 DIVM.0 SELS DIVS.1 DIVS.0 DCOR
058h
Bit0, DCOR: The DCOR bit selects the resistor for injecting current into the dc generator. Based on
this current, the oscillator operates if activated.
DCOR = 0: Internal resistor on, the oscillator can operate. The fail-safe mode is on.
DCOR = 1: Internal resistor off, the current must be injected externally if the DCO
output drives any clock using the DCOCLK.
Bit1, Bit2: The selected source for SMCLK is divided by:
DIVS.1 .. DIVS.0
DIVS = 0:1
DIVS = 1: 2
DIVS = 2: 4
DIVS = 3: 8
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BCSCTL2
Bit3, SELS: Selects the source for generating SMCLK:
SELS = 0: Use the DCOCLK
SELS = 1: Use the XT2CLK signal (in three-oscillator systems)
or
LFXT1CLK signal (in two-oscillator systems)
Bit4, Bit5: The selected source for MCLK is divided by DIVM.0 .. DIVM.1
DIVM = 0: 1
DIVM = 1: 2
DIVM = 2: 4
DIVM = 3: 8
Bit6, Bit7: Selects the source for generating MCLK:
SELM.0 .. SELM.1
SELM = 0: Use the DCOCLK
SELM = 1: Use the DCOCLK
SELM = 2: Use the XT2CLK (x13x and x14x devices)
or
Use the LFXT1CLK (x11x(1) devices)
SELM = 3: Use the LFXT1CLK
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Range (RSELx) and Steps (DCOx)
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F149 default DCO clock setting
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External Resistor
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The DCO temperature coefficient
can be reduced by using an
external resistor ROSC to source
the current for the DC generator.
ROSC also allows the DCO to
operate at higher frequencies.
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Internal resistor nominal value is
approximately 200 kOhm =>
DCO to operate up to 5 MHz.
External ROSC of approximately
100 kOhm => the DCO can
operate up to approximately 10
MHz.
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Basic Clock Systems-DCO TAPS
 DCOCLK frequency control
 nominal - injected current into DC generator
1) internal resistors Rsel2, Rsel1 and Rsel0
2) an external resistor at Rosc (P2.5/11x)
 Control bits DCO0 to DCO2 set fDCO tap
 Modulation bits MOD0 to MOD4 allow
mixing of fDCO and fDCO+1 for precise
frequency generation
Example
Selected:
f3:
f4:
MOD=19
Frequency
Cycle time
1000kHz
1000 nsec
943kHz
1042kHz
1060 nsec
960 nsec
DCOCLK
f nominal+1
Selected
f nominal
f nominal-1
DCOCLK
Modulation Period
DCO +1
+0
f0
f1
f2
f3
f4
f5
To produce an intermediate effective frequency between fDCO and fDCO+1
Cycle_time = ((32-MOD)*tDCO+MOD*tDCO+1)/32 = 1000.625 ns, selected frequency  1 MHz.
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f6
f7 fDCO
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Software FLL
 Basic Clock DCO is an open loop - close with SW+HW
 A reference frequency e.g. ACLK or 50/60Hz can be used to measure DCOCLK’s
 Initialization or Periodic software set and stabilizes DCOCLK over reference clock
 DCOCLK is programmable 100kHz - 5Mhz and stable over voltage and temperature
reference clock e.g.
ACLK or 50/60Hz
SW+HW
Controls the DCOCLK
Vcc
Vcc
Rsel
SCG0
MOD
DCO
3
0
DC-
5
Digital Controlled Oscillator DCO
DCOCLK
+
P2.5
/Rosc
1
DCOR
Generator
Modulator MOD
DCGEN
DCOMOD
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Software FLL Implementation
 Example: Set DCOCLK= 1228800, ACLK= 32768
 ACLK/4 captured on CCI2B, DCOCLK is clock source for Timer_A
 Comparator2 HW captures SMCLK (1228800Hz) in one ACLK/4 (8192Hz) period
 Target Delta = 1228800/8192= 150
CCI2BInt …
cmp
jlo
DecDCO dec
reti
IncDCO inc
reti
#150,Delta
IncDCO
&DCOCTL
;
;
;
;
&DCOCTL
; Increase DCOCLK
Delta
Compute Delta
Delta= 1228800/8192
JMP to IncDCO
Decrease DCOCLK
Target 1228800Hz DCOCLK source for timer
15
0
CCI2B
1
2
3
Stable reference ACLK/4, 8192Hz source
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Capture
Mode
0
Capture/Compare
Register CCR2
Capture
15
0
Comparator 2
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Fail Safe Operation
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Basic module incorporates an
oscillator-fault detection fail-safe feature.
The oscillator fault detector is an analog circuit that monitors
the LFXT1CLK (in HF mode) and the XT2CLK.
An oscillator fault is detected when either clock signal is not
present for approximately 50 us.
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When an oscillator fault is detected, and when MCLK is sourced from
either LFXT1 in HF mode or XT2, MCLK is automatically switched to
the DCO for its clock source.
When OFIFG is set and OFIE is set, an NMI interrupt is
requested. The NMI interrupt service routine can test the
OFIFG flag to determine if an oscillator fault occurred. The
OFIFG flag must be cleared by software.
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Synchronization of clock signals

When switching MCLK and SMCLK from one
clock source to another
=> avoid race conditions
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The current clock cycle continues until the next rising edge
The clock remains high until the next rising edge of the
new clock
The new clock source is selected and continues with a full
high period
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Basic Clock Module - Examples
 How to select the Crystal Clock
BCSCTL1 |= XTS;
BCSCTL1 |= DIVA0;
BCSCTL1 |= DIVA1;
do {
IFG1 &= ~OFIFG;
for (i = 0xFF; i > 0; i--);
} while ((IFG1 & OFIFG));
// clock is stable
BCSCTL2 |= SELM_3;
// ACLK = LFXT1 = HF XTAL
// ACLK = XT1 / 8
// Clear OSCFault flag from SW
// Time for flag to set by HW
// OSCFault flag still set?
// MCLK = LFXT1 (safe)
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Basic Clock Systems-Examples
 Adjusting the Basic Clock
The control registers of the Basic Clock are under full software control. If clock
requirements other than those of the default from PUC are necessary, the Basic
Clock can be configured or reconfigured by software at any time during program
execution.
 ACLKGEN from LFXT1 crystal, resonator, or external-clock source and divided by 1, 2,
4, or 8. If no LFXTCLK clock signal is needed in the application, the OscOff bit should
be set in the status register.
 SCLKGEN from LFXTCLK, DCOCLK, or XT2CLK (x13x and x14x only) and divided by
1, 2, 4, or 8. The SCG1 bit in the status register enables or disables SMCLK.
 MCLKGEN from LFXTCLK, DCOCLK, or XT2CLK (x13x and x14x only) and divided by
1, 2, 4, or 8. When set, the CPUOff bit in the status register enables or disables MCLK.
 DCOCLK frequency is adjusted using the RSEL, DCO, and MOD bits. The DCOCLK
clock source is stopped when not used, and the dc generator can be disabled by the
SCG0 bit in the status register (when set).
 The XT2 oscillator sources XT2CLK (x13x and x14x only) by clearing the XT2Off bit.
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FLL+ Clock Module (MSP430x4xx)
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FLL+ clock module:
frequency-locked loop clock module
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Low system cost
Ultra-low power consumption
Can operate with no external components
Supports one or two external crystals or resonators
(LFXT1 and XT2)
Internal digitally-controlled oscillator with stabilization to
a multiple of the LFXT1 watch crystal frequency
Full software control over 4 output clocks: ACLK, ACLK/n,
MCLK, and SMCLK
CPE 323
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MSP430x43x, MSP430x44x and MSP430x461x
Frequency-Locked Loop
CPE 323
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FLL+ Clock Module
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LFXT1CLK: Low-frequency/high-frequency oscillator that can be used
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either with low-frequency 32768-Hz watch crystals, or
standard crystals or resonators in the 450-kHz to 8-MHz range.
XT2CLK: Optional high-frequency oscillator that can be used with
standard crystals, resonators, or external clock sources in the 450-kHz to
8-MHz range. In MSP430F47x devices the upper limit is 16 MHz.
DCOCLK: Internal digitally controlled oscillator (DCO) with RC-type
characteristics, stabilized by the FLL.
Four clock signals are available from the FLL+ module:
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ACLK: Auxiliary clock. The ACLK is the LFXT1CLK clock source. ACLK is software
selectable for individual peripheral modules.
ACLK/n: Buffered output of the ACLK. The ACLK/n is ACLK divided by 1,2,4 or
8 and only used externally.
MCLK: Master clock. MCLK is software selectable as LFXT1CLK, XT2CLK (if
available), or DCOCLK. MCLK can be divided by 1, 2, 4, or 8 within the FLL
block. MCLK is used by the CPU and system.
SMCLK: Sub-main clock. SMCLK is software selectable as XT2CLK (if available),
or DCOCLK. SMCLK is software selectable for individual peripheral modules.
CPE 323
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FLL+ Clock Module Operation
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After a PUC, MCLK and SMCLK are sourced from DCOCLK at
32 times the ACLK frequency. When a 32,768-Hz crystal is
used for ACLK, MCLK and SMCLK will stabilize to 1.048576
MHz.
Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF
configure the MSP430 operating modes and enable or disable
components of the FLL+ clock module.
The SCFQCTL, SCFI0, SCFI1, FLL_CTL0, and FLL_CTL1 registers
configure the FLL+ clock module. The FLL+ can be configured
or reconfigured by software at any time during program
execution.
Example, MCLK = 64 × ACLK = 2097152
BIC #GIE,SR ; Disable interrupts
MOV.B #(64−1),&SCFQTL ; MCLK = 64 * ACLK, DCOPLUS=0
MOV.B #FN_2,&SCFIO ; Select DCO range
BIS #GIE,SR ; Enable interrupts
CPE 323
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LFXT1 Oscillator
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Low-frequency (LF) mode (XTS_FLL=0) with 32,768
Hz watch crystal connected to XIN and XOUT
High-frequency (HF) mode (XTS_FLL=1) with highfrequency crystals or resonators connected to XIN
and XOUT (~450 KHz to 8 MHz)
XCPxPF bits configure the internally provided load
capacitance for the LFXT1 crystal (1, 6, 8, or 10 pF)
OSCOFF bit can be set to disable LFXT1
CPE 323
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XT2 Oscillator
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XT2 sources XT2CLK and its characteristics are
identical to LFXT1 in HF mode, except it does
not have internal load capacitors (must be
provided externally)
XT2OFF bit disables the XT2 oscillator if
XT2CLK is not used for MCLK and SMCLK
CPE 323
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DCO
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Integrated ring oscillator with RC-type characteristics
DCO frequency is stabilized by the FLL to a multiple of ACLK
as defined by N (the lowest 7 bits of the SCFQCTL register)
DCOPLUS bit sets the fDCOCLK to fDCO or fDCO/D (divider). The
FLLDx bits define the divider D to 1, 2, 4 or 8. By default
DCOPLUS=0 and D=2, providing
fDCOCLK= fDCO/2
DCOPLUS = 0: fDCOCLK = (N + 1) x fACLK
DCOPLUS = 1: fDCOCLK = D x (N + 1) x fACLK
CPE 323
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DCO Frequency Range
CPE 323
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Frequency Locked Loop
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FLL continuously counts up or down a 10-bit frequency integrator.
The output of the frequency integrator that drives the DCO can be read in
SCFI1 and SCFI0. The count is adjusted +1 or −1 with each ACLK crystal
period.
Five of the integrator bits, SCFI1 bits 7-3, set the DCO frequency tap.
Twenty-nine taps are implemented for the DCO (28, 29, 30, and 31 are
equivalent), and each is approximately 10% higher than the previous. The
modulator mixes two adjacent DCO frequencies to produce fractional
taps.
SCFI1 bits 2-0 and SCFI0 bits 1-0 are used for the modulator.
The DCO starts at the lowest tap after a PUC or when SCFI0 and SCFI1 are
cleared. Time must be allowed for the DCO to settle on the proper tap for
normal operation. 32 ACLK cycles are required between taps requiring a
worst case of 28 x 32 ACLK cycles for the DCO to settle
CPE 323
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FLL+ Clock Module Registers
CPE 323
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