Transcript TIQ based ADC - Penn State School of Electrical Engineering and

HIGH SPEED CMOS ANALOG-TO-DIGITAL CONVERTER
CIRCUIT FOR RADIO FREQUENCY SIGNAL
Kyusun Choi
Computer Science and Engineering Department
The Pennsylvania State University
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Goal
Core Development and Silicon Test of
6-bit and 8-bit TIQ Based Flash ADC
1. High speed circuit and layout design
2. Prototype chip fabrication
3. Test and evaluate, explore and
improve
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Plan
1. Design 6 bit and 8 bit TIQ based ADC
circuits and CMOS layouts
2. Fabrication of prototype chip in 0.25 m
CMOS logic technology
3. Test prototype chip, extract parameters
4. Redesign 6 bit and 8 bit TIQ based ADC
circuits and CMOS layouts
5. Fabrication of prototype chip in 0.25 m
or 0.18 m technology
6. Test prototype chip, evaluate and
improve
3
Milestones
1.
2.
3.
4.
5.
6.
7.
1st Chip design, synthesis
Chip fabrication
Chip testing
2nd chip design, synthesis
Chip fabrication
Chip testing
Project presentation
12/01/2000
02/05/2001
04/06/2001
06/08/2001
08/10/2001
10/12/2001
11/30/2001
1st report
2nd report, chip
3rd report
Final report, chip
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High speed ADC applications
• Wideband RF, baseband RF, and IF signal
digitization
• Wireless point to point system
• Local multi-point distribution service
• Wireless local loop
• Computer network, universal adaptor
• Radar/communications
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TIQ based ADC
• Flash ADC
• TIQ: Threshold Inverter Quantization
• Comparator
• Inverter comparator
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Flash ADC
Vref
–
+
Vin
V1
R
V1
V2
–
+
D1
D2
D3
V2
–
+
R
V3
R
V3
Dk
–
+
R
Vn
Thermometer code to
binary encoder
Vn
Resistor ladder
circuit
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TIQ based ADC
V1
gain
booster
V2
gain
booster
V3
gain
booster
Vin
D1
D2
D3
Dk
Vn
gain booster
circuit
gain
booster
Thermometer code to
binary encoder
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TIQ Comparator
DIFFERENTIAL INPUT
VOLTAGE COMPARATOR
Vin
INVERTER
_
Vout
+
Vin
V
m
Vout
Vr
Vout
Vout
Vr
Vin
Vr is provided by a voltage references source,
External to the voltage comparator
Vm
Vin
Vm is an internal parameter of an inverter,
fixed by the transistor sizes
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Advantages of TIQ based ADC
•
•
•
•
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High speed
Less area
No resistor ladder and reference voltages
No capacitor switching
Future ready
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•
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•
Scale down
Low supply voltage
Standard digital logic technology
Ideal for SOC
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Intel’s 70-nm process takes gate to 30-nm
length Manufacturing is slated for 2005
Process name P858 P860 P1262
Production
Generation
Gate length
1999
0.18
0.13
2001
0.13
0.07
2003
0.10
0.05
P1264
2005
0.07 m
0.03 m
 Source : EE TIMES 12/11/2000
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Challenges of TIQ based ADC
• Process parameter variation
• Single ended input
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Simulation results
• 6bit at 1000 MSPS
• 8bit at 500 MSPS
• Layout area
• Power
• Process parameter variation
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Layout: 6-bit TIQ ADC
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6-bit 1 GS/s
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8-bit 500 MS/s
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Simulation results
Resolution
CMOS Technology
Power Supply
ADC Speed
6-bit
0.25 m
2.5 V
1 GSPS
ADC Area
0.013 mm2
Max Power Consumption 66.87 mW
Vm Range
0.82 V
8-bit
0.25 m
2.5 V
500 MSPS
0.075 mm2
225.8 mW
0.84 V
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Process variation
Process
Name
Start
Vm
n94s
0.6815V
n99w
End
Vm
Vm
Range
Avg.
Distance
Max.
Power
Avg.
Power
1.4999V 0.8184V
0.0132V
66.87mW
44.35mW
0.6911V
1.5030V 0.8119V
0.0131V
64.53mW
40.46mW
n99y
0.6819v
1.4808V 0.7989V
0.0129V
65.97mW
41.57mW
n9bm
0.6984V
1.4983V 0.7999V
0.0129V
65.30mW
41.70mW
t02b
0.6874V
1.5288V 0.8414V
0.0136V
72.29mW
46.51mW
t02d
0.6955V
1.5188V 0.8233V
0.0133V
71.48mW
45.29mW
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Innovation challenges
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2 GSPS with 0.18um CMOS
Custom layout CAD tool
10bit and 12bit ADC
Low power
Dynamic calibration
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Offset
Gain
Temperature
Power supply voltage
Process parameter variation
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Summary
• High speed ADC for RF
• ADC core - 6bit and 8bit design
• prototype chips (silicon test)
• 0.25 m (or 0.18 m)
• CMOS digital logic technology
• Future ready
• Dynamic calibration
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