Transcript Active Region - UniMAP Portal

Basic MOS Device Physics
1
Concepts
understanding of semiconductor devices is
essential in analog IC design
Performance affected by second order effects,
often neglected in digital design
More for deep submicron technologies
Develop transistor model for circuit
performance and analysis
MOS structure, IV characteristics, second order
effects, parasitic capacitances, small-signal
model for MOSFET ,SPICE model
2
MOS Device Structure
4-terminal device, with S and D
interchangable
Digital IC: transistor acts like a switch
Turns on (S and D “connected together”)
when VG high, off when VG low



Structure:
2 heavily-doped n regions defining D and S,
heavily-doped polysilicon forming G, thin layer
of oxide insulating G from substrate
Useful action occurs in substrate region under
gate oxide
3
NMOS and PMOS
with Well
CMOS – both NMOS and PMOS available
on the same substrate
Ok for NMOS, but PMOS must define a local nsubstrate -> n-well
NMOS: S/D junction must be reverse-biased ->
substrate connected to most negative supply voltage
PMOS: S/D junction must be reverse-biased ->
substrate connected to most positive supply
4
MOS Symbols
5
triode region I-V characteristic
ID  nC
W
ox
L
1
[(VGS  V TH)VDS  VDS 2 ]
2
Triode region when VDS <= VGS - VTH
6
Operation in Triode Region
1
2
ID  nC
[(VGS  V TH)VDS  VDS ]
2
W
ID  nCox L (V GS  VTH )VDS, V DS  2(V GS  VTH )
W
ox
L
-> ID linear function of VDS
Parabola approximated by
straight line.
S-D can now be modelled as
a linear controlled-resistor given by
VDS/ID and value controlled by overdrive voltage (VGS – VTH)
1
RON 
W
n Cox L (VGS  V TH)
7
Active Region (cont.)
Active Region
8
Operation in Active
(Saturation) Region
 If VDS > VGS-VTH?
 I/V curve no longer parabolic
 ID constant, device in saturation/active region
 Density of inversion layer proportional to VGS – V(x) – VTH
 If VDS slightly greater that VGS – VTH, inversion layer stops at x <= L;
i.e. channel is pinched off
 As VDS increases further
 Point at which Qd equals zero gradually moves toward S
1
ID  nC
[(VGS  V TH)VDS  VDS 2 ]
2
'
V DS  V GS  VTH (Pinch  off )
nCox W
ID 
(V GS  VTH )2
2 L
W
ox
L
9
Drain current characteristics
10
Drain current
Linear region (Vds < Vgs - Vt):
Id = k’ (W/L)(Vgs - Vt)(Vds - 0.5 Vds2)
Saturation region (Vds >= Vgs - Vt):
Id = 0.5k’ (W/L)(Vgs - Vt) 2
11
MOS operation conclusion
region
VG
ID
VDS condition
condition
OFF
VG < VTH
Any value
TRIODE/
LINEAR
VG >VTH
VDS < VDS -VTH nCoxW/L (VDSVTH)VDS – 0.5VDS2
SATURAT
ION
VG >VTH
VDS > VDS -VTH 0.5nCoxW/L (VDSVTH)2
0
12
Transconductance, gm
 Let’s define gm as an indicator of how well a device
converts a voltage to a current (consider saturation
region)
ID  nCox W (VGS  V TH)
L
gm 
VGS VD S cons tan t
 gm represents device sensitivity
gm  2 nCox L ID
2ID

VGS  V TH
W
e.g. small change in VGS results in large change in ID
As seen in eqn above, gm is equal to inverse of Ron in deep
triode region
13
gm behavior – from gm plot
Notice:
gm increases with overdrive if W/L constant
gm decreases with overdrive if ID constant
14
Triode and Active Region Transition
Rule of thumb when trying to know if device
is in saturation or linear
NMOS: VG - VD < VTHN, pinch-off occurs
PMOS: VD – VG < |VTHP|, saturation
Active
Active
15
Second-Order Effects
Now let’s look at second order effects and
get some idea on how our circuit could be
affected by the phenomena
16
Body
Effect
 What happens when bulk and source are not at the same
potential
 Consider NMOS: When VB drops below VS
 S and D still reverse-biased -> device continues to operate properly
but some device properties might change
 e.g. VS=VD=0; VG a bit less than VTH -> depletion layer formed but
no inversion layer
 As VB becomes more negative -> more holes attracted to substrate
connection, leaving larger –ve charge behind (i.e. depletion region
becomes wider)
 VTH = f(total charge in depln region), and gate charge must mirror Qd
(channel charge density) before an inversion layer formed
 VB drops, Qd increases, VTH increases -> “Body effect” / “Backgate”
Effect
VTH  V TH0    2F  V SB  2F  ,  
2qsiNsub
Cox
17
Body Effect …
VTH
Qdep
 MS  2F 
Cox
l denotes body effect coefficient
Typical values: 0.3 to 0.4V1/2
Could take place when:
Bulk potential change
Source potential varies wrt bulk potential
18
VTH and Body Effect
 Ignore body effect:
No Body Effect
With Body Effect
 As Vin varies, Vout closely follows the input
 Drain current remains I1
• I1=0.5nCox(W/L)(Vin-Vout-VTH)2
• i.e. (Vin-Vout) is constant if I1 is constant
 Body effect significant, substrate tied to gnd
 As Vin and Vout become more positive
 VSB increases -> VTH increases
 To maintain constant ID, Vin-Vout must increase as well
 Body Effect: Undesirable, complicates design of analog and
digital Ics
 Nsub and Cox has to be balanced for reasonable l device
engineers’ job!!!)
19
Channel Length
Modulation
L
L’
Noted earlier that VGD L’ (pinch-off)
L’=f(VDS)  channel length modulation
1
1
/
L
'

(1  DL / L)
We can then write: L'  L  DL

L
st
Assume 1 order relationship btwn DL/L and VDS,
and define l as CLM coefficient:
1
1/ L'  (1  lVDS ), l VDS  DL / L
L
We can re-write current equation in saturation:
ID 
nCox W
2
L
(V GS  VTH )2 (1  lV DS )
20
Channel Length Modulation
(cont’d…)
 CLM results in non-zero
slope in IV characteristics
 Non-ideal current source btwn D and S in saturation regime
 l represents relative variation in length for a given increment in VDS
 Short channel -> must consider bcoz it’s bigger compared to longer
channels
 DL/L  VDS linear approximation becomes less accurate for shorter
channel
 Re-write equation for current in saturation -> must rewrite equation
for transconductance, gm
2 nCox W L ID
W
gm  nCox (V GS  VTH )(1  lV DS ) gm 
(1  lVDS )
L
2ID
gm 
, (unchanged)
VGS  VTH
21
Subthreshold Conduction
 When VGSVTH, weak inversion layer still exists
(transistor do not fully turn off)
hence allowing some current flows from D to S
ID drops at a finite rate as VGS falls below VTH

VGS 
ID  I 0 exp 
kT 
z

q
 Exponential dependence on VGS
 z > 1 = nonideality factor, VT=kT/q
 Eqn similar to bipolar’s characteristic
 Subthreshold Conduction:
Subthreshold conduction
Static Power Dissipation (Leakage)
 a problem for large circuits (e.g. memory)
22
MOS Layout
 Brief look at layout to better understand / visualize
device capacitance & MOS model
 Layout determined by:
Electrical properties required of the device & design rules
(e.g. W/L dictates gm, L governed by the process)
 (a) 3D view of an NMOS
 (b) top-view
Poly extends beyond diffusion
 Ensure reliable definition of edge of transistor
 Total S and D area minimized to minimize capacitance
23
Layout…
Draw layout of circuit in (a)
24
Device Capacitances
Need to consider to predict ac behavior
Value of capacitance depends on bias
conditions of transistor
Source of capacitance:
Oxide capacitance, Cdepln, Coverlap
25
Device cap… cont’d
 Oxide capacitance
 Btwn gate and channel
 C1 = WLCox
 Depletion capacitance
 Btwn channel and substrate
 C2 = WL(qsiNsub/(4fF))
 Overlap capacitance
 C3 and C4, simplest formula WLDCox
 More elaborate calculations required for accurate value
 Junction capacitance
 Btwn S/D and substrate
 Cbottom-plate (Cj) + Cside-wall (Cjsw)
 Cj = Cjo/[1 + VR/fB]m, VR = reverse voltage across junction, fB built-in26
potential, m a power in between 0.3 and 0.4
Layout for Low Capacitance
 Folded structure
 For layout in (a)
C DB  C SB  WEC j  (W  2 E )C jsw
 For the same transistor in (b)
W
C DB  EC j  2( E )C jsw
2
W
W

C SB  2 EC j  2(  2 E )C jsw 
2
2

 WEC j  (W  4 E )C jsw
 Note: (b) has less CDB than (a)
27
G-S and G-D
Capacitance
 Device off
 CGD = CGS = CoverlapW
 CGB = Cox in series with Cdepln
 CoxCdepln/(Cox + Cdepln)
 Device in deep triode region (VS  VD)
 CGS = CGD = Cox/2 + overlap cap = WLCox/2 + Wcov
 Cox/2 because WLCox divided equally btwn GS and GD terminals
• Change DV in VG draws equal amount of charge from S and D
 Device in saturation
 CGD  Wcoverlap
 Non-uniform vertical electrical field in gate oxide along channel because
 Potential across channel varies from VGS @ S to VGS – VTH at pinch-off point
 CGS = 2WLeffCox/3 + Wcoverlap
 CGB neglected in triode & saturation because inversion layer acts as shield
btwn G and bulk. Charge supplied by S and D rather than bulk for a change in
28
DVG
MOS Small Signal Models
Channel length
modulation modeled as
aVDS
Channel length
modulation modeled
as a resistor
Body effect modeled as
gmVBS
29
Models explained…
Channel Length Modulation
ID varies with VDS -> modeled by a voltagedependent current source
Note: I linearly varies with V -> linear resistor
VDS
1
1
1
ro 




n
C
ox
W
ID ID / VDS
lID
(VGS  VTH ) 2 l
2
L
ro affects circuit’s performance
Limits amplifier gain, affect output impedance, etc.
30
Bulk Transconductance, gmb
 Bulk potential affects VTH hence gate-source overdrive
 When all other terminals held constant
 ID = f(VB) -> bulk behaves like a second gate
 Modeled as a dependent current-source -> gmVBS
ID nCox W
 V TH 
gmb 

(V GS  VTH )
 V BS 
V BS
2 L
saturation
Also,
VTH VTH


  (2F  V SB)1/ 2
V BS
VSB
2

gmb  gm
 gm
2 2F V SB
fF = work function of polysilicon
gate – work function of
silicon substrate
fF = (kT/q)[ln(Nsub/ni)]
31
Gate Resistance
Need to consider resistivity
as well
Each terminal exhibits finite ohmic resistance
How to minimize the resistance?
Folded structure?
Reduces RG by 4X
32
MOS Small Signal Model with
Capacitance
33
C-V of NMOS
 Capacitor on chip very expensive
 Transistor capacitive (monolithic)
 NMOS: S,D, and bulk GND-ed
 VG inversion layer forms from VGS  VTH
 For VG –ve
 Holes in substrate atrracted to oxide interface
• NMOS in “accummulation region”
 Device viewed as Cox (gate plate and substrate plate, tox separation)
 As VGS density of holes @ interface falls
 Depletion region starts to form, device enters weak inversion
 C = Cox and Cdepln
 For VGS > VTH
 Channel formed. Capacitance = Cox
34