Transcript Automated Analog Circuit Design

Automated electronic design
By Alexander Mitev
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4.
5.
Introduction
Area of problems
Approaches and solutions
Other related Ideas
Conclusions
Introduction
• - Why to automate ?
• - Time cycles, cost, quality
• - Computer design vs. hand made
Introduction
• - Digital vs. Analog
Circuit scale
Design methodology
Design
Synthesis system
Behavior of the
transistors
Salary
DIGITAL
ANALOG
LARGE
SMALL
VHDL
SCHEMATIC
SYSTEMATIC
INTUITIVE
CURRENTLY USED
NOT YET
SIMPLE
COMPLEX
HIGH
HIGHER???
Introduction
• The art of analog circuit design
Area of problems
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Complex behavior of analog circuits
No common rule how to synthesize
The imperfection of computer modeling
The rising complexity of formal solutions
The highest degree of freedom of analog
circuits
• Mostly the solutions in analog design is
approved after simulation or real test.
Available solutions – Genetic
programming
-Achieves this goal of automatic programming by genetically breeding a
population of computer programs using the principles of Darwinian
natural selection and biologically inspired operations.
-Genetic operations include reproduction, crossover (sexual
recombination), mutation, and architecture-altering operations
patterned after gene duplication and gene deletion in nature.
-The main generational loop of a run of genetic programming consists
of the fitness evaluation, Darwinian selection, and the genetic
operations.
Available solutions – Genetic
programming
-Genome – a collection of genes , representing parameters
of the problem to be optimized
- Example of genome:
1 0 1 0 0 1 1 0 1 0 0 0
Input Resistor Ro
Transistor
Width
Output Impedance
Available solutions – Genetic
programming, example 1
• Goal – Best solution for the transistor widths and resistor value for R1
• Genome – 76 bit , approximately 7.5x1025 possible designs
Available solutions – Genetic
programming, example 1
• Results:
• Result in 163’th generation
• Total work time: Pentium 200 - 15 min
Available solutions – Genetic
programming, example 2
• Goal – Filter Synthesis
• Limitation: bandwidth, minimal component
• Fitness calculation:
Fitness 

i 100.. F
W ( d ( f i ), f i )
d ( f i )  VGOAL ( f i )  VOUT ( f i )
W
1, d ( f i )  W
10, d ( f i )  W
Available solutions – Genetic
programming, example 2
L7
1m
C10
1u
VOUT
L6
C9
C11
1u
R12
1u
1K
L8
1m
1m
R9
1K
R11
1K
C8
1u
C4
1u
C5
1u
C7
1u
R5
1K
R14
1K
R7
R13
1K
0
V2
L4
1m
1K
R6
R8
1K
1K
Best individual at generation 40
R10
1K
Available solutions – Genetic
programming, example 2
Fitness
Elements
34 elements
0.0001
50
100
150
5 elements
50
100
150
- Solution after the 100’th generation
- Minimal elements and exact pass bandwidth.
- Total CPU time - 7h 43min.
Generation
Available solutions – Genetic
programming, example 2
R2
C2
1u
1K
VOUT
R3
R4
0
1K
1K
VIN
C3
1u
L3
L2
1m
1m
Available solutions – Genetic
programming, example 3
Goal Low pass filter using parallel GA
- Genome 400 bytes ; 18000 individuals max
- Best result 23’th generation
- Total working time 6 SUN workstation 4 hours
-
Available solutions – Genetic
programming: Summary
-Benefits:
-Novel approach by simulating natural selection
-Mostly with GA could be solved problems faster than
by hand.
Shortcoming (regarding this research)
-Time dependable
-Domain dependable, presently available for filters and
amplifiers
-No guarantee to solve the problem
Available solutions – Automated
design by reusing
• CBR: the basic idea is to solve a new problems by
comparing them with old ones that have been solved in
the past
• Major method – testing for similarity.
• Base with “past experience”, Intelligent retrieval
• Intelligent retain – if a new solution is available
• Generalizing this idea by considering the common sense
of Intellectual product (IP)
The reuse - cycle
- Retrieval – an IP is selected
corresponding to the respective
specifications
The reuse - cycle
- Retrieval – an IP is selected
corresponding to the respective
specifications
- Instantiation: If an IP has been selected
the necessary design is instantiated, OR
The reuse - cycle
- Retrieval – an IP is selected
corresponding to the respective
specifications
- Instantiation: If an IP has been selected
the necessary design is instantiated, OR
- The design flow is defined to meet the
constraints
The reuse - cycle
- Retrieval – an IP is selected
corresponding to the respective
specifications
- Instantiation: If an IP has been selected
the necessary design is instantiated, OR
- The design flow is defined to meet the
constraints
- Retain – if it has been decided to store the
synthesized circuit
Solution – Reuse
Design by reuse
• Algebraic description of Libraries
• Basic requirement : LB, LF library
Kb – behavior to be synthesized
Vb – behavior parameters
Db- allowed parameters
Kf – design flow to be synthesized
Vf – des. flow parameters
Df- allowed des. flow parameters
Design by reuse
LB library – parameterized design
LB – store certain design, which can be
instantiated
Kb – parameterized specification of the
synthesized behavior
Vb – specification parameters
Db – allowed parameters
Design by reuse
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Specifications b and b’ are:
- identical
- equal (same behavior)
- extension b<b’
• Example 32 bit adder and 16 bit adder
Design by reuse
• LF library – design flow for synthesis
LF – store certain design flow
Kf – parameterized design flow
Vf – specification parameters
Db – allowed parameters values
Design by reuse
• Algebraic description of Libraries
• Reuse library LIB
Ki – parameters for behavior and des. flow
Vi – both parameters from Vb and Bf
Di- allowed parameters values
Ki  ( Kb, Kf );
Vi  Vb  Vf ;
Di
Design by reuse
• Reuse component IP I = (Ki, Vi, Di)
• Instance if |Di|=1
• Configurable if |Di|>1
Ki – parameters for behavior and des. flow
Vi – specification parameters from Vb and Bf
Di- allowed parameters values
Design by reuse
Design by reuse
Design by reuse
• Similarity of IP’s
simV : d I (v )  d I ' (v )  [0.1]
SIM ( I , I ') 

v(VI VI ' )
rv simV (d I (v ), d I ' (v ))  (0,1]
For each parameter in Vi is calculated similarity of the allowed parameters
Rv – relevance factor, stating the importance ov V for the hole design
Design by reuse
• Constraint management
Pd max
Pd max
Id max
Rds max
Rds max
Pdrain  f ( Id , Rd )
Id max
Design by reuse
• Constraint management
Pd max
Pd max
Id max
Rds max
 Rds
Rds max
Pdrain  f ( Id , Rd )
Id min
Id max
Design by reuse - example
• READEE project – CBR technology of design and IP
reuse
• Realization as a WEB based service.
• Problem domain – selection of DSP processors
• Similarity measure – application and DSP-specific
information ( Example : consuming power )
• Performance or qualifying is based on abstract table
model including many application orientated properties
Design by reuse - example
• DSP operations table:
• 1. Operations , such as arithmetic, logic etc.
• 2. Performance profile : filter (parameters) ; FFT
(parameters, #simples) ; general purpose options
• Task of evaluation model supporting similarity
calculations:
• 1. Clock frequency is derived as a function of consuming
power
• 2. User specified performance profile is mapped to the
main data code.
Design by reuse - example
DSP function taxonomy
Design by reuse - summary
Benefits:
- Knowledge based approach
- No iterations, quick solution (if there is a solution)
- With retain mechanism – theoretically provide
solutions for all possible problems
Drawbacks:
1. Design for reuse
2. Numerous parameters, one another dependable
3. In many cases scalable design is impossible
Design by reuse
• Define domain of problem set (ex. Noise, gain etc.)
• Determine all domain of parameters ( ex. frequency,
resistance, etc).
V – V [p1, p1, ….pn]
• Level-1: L1 base - Separate the Analog circuit in simple
modules with known parameters (ex. Transistor, capacitor
etc).
L1- L1[Ti, Vi]
• Leve-2 : L2 base – Topological low level description (CE
transistor, Differ. Pair.)
L2 – L2(L1k, Vk)
Design by reuse
• Hence we have description of all analog
building blocks
• The instantiate base describes all available
design circuits
• Now we can reuse different block according
problem specification
I (t )  F [ L2(k ),V ( r )]
Design by reuse
Simplifying of circuit by substitution with building blocks
1
VCC
10
C1
100pf
RC2
C
5K
RC1
5K
L1
100uh
Q1
beta= 100
Q2
Q3
beta= 100
beta= 100
Q4
2
beta= 100
VLO
0
A
A
B
B
3
Q5
Q6
beta= 100
beta= 100
IEE
300ua
VBIAS
-2
VRF
0
4
Ideas for automated electronic
design
• By decomposition the circuit into submodules or
building blocks we can get these advantages:
• 1. instantiate each block, not the hole circuit
• 2. if we symbolic describe behavior of each block we
can make some prediction of the total behavior of the
circuit. More important is the reverse operation – to
make a relation from behavior to building modules.
Ideas for automated electronic
design
• 3. If we can make a complete set of building blocks. It
will be one step ahead to use one special case of reuse
– software reuse similar to HDL based languages.
Presently is available analog extension of VHDL but only
for elementary elements ( transistors, diodes)
• Problems :
– Rising complexity of symbolic representation with the
size of circuit
– Every circuit maintain one symbolic representation,
but not vice versa.
Conclusion, feature work
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4.
The key of the analog design is in distinguishing of the
topologies.
Common ontology for analog design. (not seen yet in
the topic of automated analog design). Example: Hi-Fi
audio amplifier includes: filters, amplifying modules,
comparators etc).
Each element of this ontology has to be provided with
detailed parametric specifications: - all allowed
parameters ; - all scalable parameters.
We can reuse the elements not the hole circuit
Conclusion, feature work
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4.
Scenario for design flow could be possible to simulate
based on the symbolic description (expression) of the
problem by evaluating and/or reusing.
Mechanism for decomposition major problem to minor
subproblems.