Transcript ECE 601 - Digital System Design & Synthesis Lecture 1

ECE 551 - Digital System Design & Synthesis
Lecture 2 - Pragmatic Design Issues
Overview

Miscellaneous problems that arise in design and
their solutions

Classification of Issues
o
o
o
o
o
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Three-State and Other Hi-Z States
Sequential Circuit Basics
Asynchronous Circuits
Clock Design
Electrical Issues
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Three-State and Other Hi-Z
States
Three-state conflicts
 Floating three-state nets and inputs
 Pull-ups and Pull-downs
 Bus keepers

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Three-State Conflicts

What are they and what are their effects?
o Static – Chip damage
or static power consumption
o Dynamic – Dynamic or static
power consumption
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D0
1
E0
0
D1
1
E1
E0 1
E1 1
1
E0 0
E1 01
OUT
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Three-State Conflicts
(continued)

How can conflicts be avoided?
o Static – Decoded enable
signals
o Dynamic – Delay control
1
0
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1
E0 0
E1 01
D0
E0
1
E0 0
E1 1
OUT
D1
E1
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Floating Inputs and ThreeState Nets

Floating input values on gates can cause:
o static power dissipation
o high-frequency switching that induces power supply
noise

Floating input values arise from:
o Gate inputs, e. g., for example on exterior of IC, that
are not connected
o Lines driven by 3-state buffer or gate outputs, all of
which are in the Hi-Z state.
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Floating Inputs and ThreeState Nets (continued)
 How
can floating inputs and nets be
avoided?
o Use a pull-up or pull-down resistor or
transistor with a fixed gate voltage value.
 Advantage – simple
 Disadvantages – static power dissipation and
loading of node
o On internal lines, particularly buses, use a bus
keeper (weak buffer)
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Sequential Circuit Basics
 Non-D
flip-flops
 System
initialization process
 Mixed-edge
clocking
 Multi-phase
clocks
 Multiple
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clocks
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Non-D flip-flops

D Flip-Flops
o Unique characteristic – the typical master-slave DFF
is also functionally an edge-triggered DFF.

Non- D Flip-Flops (JK, T, etc.)
o In the cell libraries, these flip-flop may be full-custom
designs or may simply consist of a DFF with added
logic.
o If it is just a DFF with added logic, you might as well
design for a DFF to give the logic optimization
software more flexibility.
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System Initialization
Process
 Flip-flop
initialization
o Occurs at power-up or at reset
o Which of the following flip-flops need to be
initialized immediately on power-up or reset:
 Sequencing circuit in the control unit?
 Register file in the datapath? No
 Program counter? Yes
Yes
o How are the other flip-flops initialized?
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System Initialization
Process (continued)
 Flip-flop
initialization
o How are flip-flops initialized?
 By using direct set and direct reset inputs on the
flip-flops (typically need only one or the other)
 Suppose that a FF is to be initialized to 1 and
there are only library cells with with direct reset.
What can you do?
D Q
D
Q
C R
CLK
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RESET
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Mixed-Edge Clocking

Clocking on both:
o Positive and negative edges, or
o Positive and negative pulses

In some cases may be useful to:

o Obtain two event triggers per clock cycle
o Deal with certain nasty timing problems such as hold
time difficulties
Confusing and more difficult to handle when using tools
Quantizes time and adds FF delay time much as
pipelining does, so can reduce speed unless throughput
is the issue as with pipelining

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Multi-Phase Clocks
 Uses
F1
C
L
F1
F2
Latches
C
L
Latches
o As primary clocking approach using latches
o As means to solve special timing problems
F2
CL - Combinational Logic
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Multiple Clocks
 Typical
in sophisticated circuit
 Example - Microprocessor
o 133 MHz External
o 1 GHz Internal
 Potential
for synchronization problems
between clocking domains
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