Transcript VLSI_final powerPoint

Final Lesson
•
ESD
• Summary VLSI Technologies
ESD
The gate oxide in CMOS transistors is extremely thin (100 Å or less). This
leaves the gate oxide of the I/O cell input transistors susceptible to
breakdown from static electricity ( electrostatic discharge , or ESD ). ESD
arises when we or machines handle the package leads (like the shock I
sometimes get when I touch a doorknob after walking across the carpet at
work). Sometimes this problem is called electrical overstress (EOS) since
most ESD-related failures are caused not by gate-oxide breakdown, but by
the thermal stress (melting) that occurs when the n -channel transistor in an
output driver overheats (melts) due to the large current that can flow in the
drain diffusion connected to a pad during an ESD event.
To protect the I/O cells from ESD, the input pads are normally tied to device
structures that clamp the input voltage to below the gate breakdown voltage
(which can be as low as 10 V with a 100 Å gate oxide). Some I/O cells use
transistors with a special ESD implant that increases breakdown voltage and
provides protection. I/O driver transistors can also use elongated drain
structures (ladder structures) and large drain-to-gate spacing to help limit
current, but in a salicide process that lowers the drain resistance this is
difficult. One solution is to mask the I/O cells during the salicide step.
Another solution is to use pnpn and npnp diffusion structures called siliconcontrolled rectifiers (SCRs) to clamp voltages and divert current to protect
the I/O circuits from ESD.
ESD Cont.
There are several ways to model the capability of an I/O cell to withstand
EOS. The human-body model ( HBM ) represents ESD by a 100 pF
capacitor discharging through a 1.5 kohm resistor (this is an International
Electro technical Committee, IEC, specification). Typical voltages
generated by the human body are in the range of 2–4 kV, and we often
see an I/O pad cell rated by the voltage it can withstand using the HBM.
The machine model ( MM ) represents an ESD event generated by
automated machine handlers. Typical MM parameters use a 200 pF
capacitor (typically charged to 200 V) discharged through a 25 ohm
resistor, corresponding to a peak initial current of nearly 10 A. The
charge-device model ( CDM , also called device charge–discharge)
represents the problem when an IC package is charged, in a shipping tube
for example, and then grounded. If the maximum charge on a package is
3 nC (a typical measured figure) and the package capacitance to ground
is 1.5 pF, we can simulate this event by charging a 1.5 pF capacitor to 2
kV and discharging it through a 1 ohm resistor.
VLSI Technologies
CMOS: Integration,Memory, Power diss, Input Impedance
(Composition),Cost
Bulk: Logic, Mixed Signal, Analog, Embedded (DRAM,Flash,EEProm)
SOI: Lower Voltage/Power dissipation , Less Substrate Noise, Smaller
Layout, Eliminates latch up&High energy implanter
HV/LV: Standard , Up to 100V/5V
BiCMOS:
Integration, Speed,Memory, Power diss,
Input Impedance, Drive, Noise
Bipolar:
Speed, Drive, Noise, Cost
Non Silicon: SiGe (Emerging: BiCMOS: Integration ) ,
GaAs (BJT, better Ft)
HomoJunction & HetroJunction Transistors (HBT better: Emitter
efficiency,lower Base Res. >> Freq. response, temp range)