Transcript R FLT - TI E2E Community

Selecting the Right Amplifier
for a
Precision CDAC SAR A/D
-
?
+
A/D
Digital
Out
VIN
Tim Green (HPL Linear)
With Insights from: Bill Klein (HPL Linear), Rod Burt (HPL LInear),
Bernd Rundel (HPL DAP), Rick Downs (HPL DAP), Bob Benjamin (HPL DAP) 1
Factors of Concern
Power Supply Rails
Size of LSB
Offset
Drift
Noise
Bandwidth
Distortion
A/D Architecture
Target Example:
+5V, 16-Bit, 100kHz, CDAC, SAR, A/D Application
2
Power Supply Rails
 Bipolar
+/- 15V
 Implies:
+/-10V signals

Single Supply
+5V
+3.3V
+1.8V
Signal
ranges:
+1.5V to +5V
3
LSB Size
Signal range is critical

+/-10V is a 20V range
 12 bits: 20V/4,096 = 4.88mV per LSB
 16 bits: 20V/65,536 = 305µV per LSB

+5V range
 12 bits: 5V/4,096 = 1.22mV per LSB
 16 bits: 5V/65,536 = 76.2µV per LSB
 24 bits: 5V/16,777,216 = 298nV per LSB

+3.3V range
 12 bits: 3.3V/4,096 = 806µV per LSB
 16 bits: 3.3V/65,536 = 50.4µV per LSB
 24 bits: 3.3V/16,777,216 = 196nV per LSB
4
DC Parameters
 If all you have to work with is 38µV (1/2 LSB)…

Offset Voltage becomes significant
 Offset from differential bias current, too!

OPA335 as an example
 Single Supply
 Input offset less than 20µV
 Temperature Changes


If your system has to operate from -25°C to +75°C, you have a
100°C range of temperature change.
If all you have is 38µV (1/2 LSB)…
 And 20 µV is used up by offset, then you have 18 µV allowed for drift, so you can
handle 180nV/°C of drift
 Note: Offset effect may be compensated in the
system software!
5
AC Parameters
 Noise - depends upon bandwidth

Resistor noise
4KTRB
 1K ohm resistor = 579nV @ 25°C, 20kHz bandwidth.



Current noise
Voltage noise
Sampling Noise of A/D > Tens of μVolts
 Distortion


THD+N of a 16-bit converter should be better than -98dB, or
0.0011% - again, over the bandwidth of interest.
Suitable op amps:
 OPA627(Dual Supply)
 OPA350, OPA134 (Single Supply)
 Single Supply Op Amps

As common mode voltage changes, op amp passes through
different regions of bias - this results in something similar to
crossover distortion
6
Single Supply RRI Plot - VOS vs CMV
(Most RRI Op Amps Except OPA363/OPA364)
OPA2340 (Dual: VOUT1 & VOUT2 from different halves)
Gain=X100
Diff Amp
Configuration
CMV
CH1
VOUT1
CH2
VOUT2
CH3
7
Single Supply RRI Alternate
Avoids CM Input “Crossover”
Inverting “Buffer”
Filter
A/D
+5V
0V
0V
RF
CFLT
F
R
R
RB1
=
=
R
R I =
1
B2
=1
+5V
+2
.5
V
V
RB2
Digital
Out
+
CM
=
RFLT
B1
I
IN
Z
VIN
+5V
-
=
R
RI
Vnoise
8
Single Supply Inverting “Buffer”




ZIN is RI (typically < 100kΩ) instead of >100MΩ range
VOUT of Buffer is Inverted from VIN
VCM does not move and is steady at 1/2VCC
Mismatch in ratios of RF / RI = 1 and RB1 / RB2 = 1

Gain & Offset Errors
 RI, RF, RB1, RB2 are additional noise sources
9
Input Buffer Selection
V
A/D
RFLT
-
?
+
100
?
CFLT
?
VIN
?
RSW
t
VCC ?
1/2VCC ?
GND ?
SWSAMPL
CSH
20pF-40pF
VREF
SWCONV
 Charge injection causes large spike which must settle in tSAMP.
 Adding a capacitor (and possibly a resistor) can reduce spike
 Op amp must be capable of charging capacitance in tSAMP to
0.5LSB. Low output impedance at high frequency required.
 OPA627 (Dual Supply), OPA350 (Single Supply)
10
What Settling Time?
 Think of a linear voltage regulator –
There are TWO Settling Times.


Line Transient
Load Transient
Line
Transient
+15V
Load
Transient
Linear
Regulator
+5V
VOUT
VIN
RL
11
What Settling Time?
 Similar to Linear Regulator
Line Transient =
Input Step Voltage;
Output Voltage Slew Rate
Load Transient =
Output Step Voltage;
Output Step Current
Line
Transient
+
VIN
+
Load
Transient
VOUT
IT
CL
12
Settling Time
Number of bits
10
12
14
16
18
20
22
24
0.5LSB
0.0488281%
0.0122070%
0.0030518%
0.0007629%
0.0001907%
0.0000477%
0.0000119%
0.0000030%
Time Constants
8
9
11
12
13
15
17
18
13
Op Amp “Line Transient”
Response to change in input signal
Includes Slew Rate.
Op Amp data sheets MAY address
Settling Time to 0.01%
But we need 0.0007629% for a 16 bit
system
14
“Load Transient” is WORST
We know the load is the input
capacitance of the A/D (CSH)
We do NOT know the starting voltage
on CSH.

Possible voltages: GND, Mid-Rail, Random
The Op Amp data sheet does NOT
even mention “Load Transient”
response.
15
System Design Variables
Op Amp
Filter
A/D
-
Digital
Out
+
VIN
Op Amp
Filter
Noise, Signal BW,
Noise Filtering,
Acquisition Time,
CMV Range, Slew Rate,
Cload Isolation,
Architecture (CDAC SAR)
Output Impedance, Settling Time,
Charge Bucket
Power Supply,
Load Transient, Gain Error,
(Flywheel)
Data Rate, Resolution,
Power Supply, VOS vs CMV Input,
Circuit Topology, THD + Noise
ADC
ADC Input, ADC Ref In
16
SAR A/D < 500kHz
 70% Applications



Slow Moving “Real World Process” Signals
Fast Acquisition & Conversion Allows More System Time For
Processing, Computation, Decision Making
Multiplexed, Scanning Systems for Slow Moving Signals
 30% Applications


AC Fast Moving Dynamic Signals
“Real Time” Processing of Input Signals
 Assume for our analysis that during sample time VIN is
constant
17
Analysis By Example
Op Amp
A/D
Filter
+5V
+5V
+5V
+
VIN
+VREF
?
+VCC
ADS8320
RFLT
?
DOUT
CFLT
?
4.87Vpp
(65mV to 4.935V Swing)
1kHz
18
Analysis Will Use
Tricks
Data Sheet Parameters
Factory Only Parameters
Rules of Thumb
Testing
19
A/D Converter Terms
 Acquisition Time (tSMPL):

The time the internal A/D sample capacitor is connected to the A/D input.
 Conversion Time (tCONV)

The additional time the A/D requires to convert the analog input to a
digital output after the acquisition time (tSMPL) is complete.
 Throughput Rate [Sampling Rate]

Maximum frequency at which A/D conversions can be repeated
 i.e. 100kHz Throughput Rate [Sampling Rate] implies that an input analog
signal may be converted every 10μs.
20
Standard ADS8320 Timing
tSMPL= 4.5 Clk Cycles min
21
A/D tSAMPL Trick
2x tSAMPL= 84% Throughput Rate
Sample
CS/SHDN
System Clock
DCLOCK
System Clock
(SCLCK)
DCLOCK
tSMPL
tCONV
tpower down
Throughput Rate
2.4MHz
System Clock
4.5 SCLKs
1.87ms
16 SCLKs
6.67ms
3.5 SCLKs
1.46ms
100kHz
2.4MHz
Modified System Clock for
tSMPL = 9 System Clock Cycles
9 SCLKs
3.75ms
16 SCLKs
6.67ms
3.5 SCLKs
1.46ms
84kHz
22
ADS8320 Application Specs










“16 Bit, High Speed, 2.7V to +5V, micropower sampling A/D”
VCC = +5V, VREF = +5V
Throughput Rate (Sampling Rate) = 100kHz
DCLOCK = 2.4MHz, tSAMPL=1.88μs
Input Signal = 4.87VPP (65mV to +4.935V range),1kHz max
SNR = 88dB @ 1kHz
THD = -86dB @ 1kHz
SINAD = 84dB @1kHz
SFDR = 86dB
ENOB = 14.33
23
OP Amp Buffer Application Specs
 Application:









Single Supply = +5V
Buffer – NO CM Input Crossover !
Slew Rate to track 1kHz Input
Wideband for good gain flatness: 1kHz, G=1
Wideband for fast transient response to Noise Filter Transients
Low Noise for 16 Bit performance
Fast Settling time for output transients
Adequate Output Drive Current for Filter Transients
RRIO for 65mV to +4.935V Input and Output on +5V Supply
 Best Industry Choice
 OPA363 or OPA364 (OPA363 with Shutdown feature)
 “1.8V, 7MHz, 90dB CMRR, Single-Supply, Rail-To-Rail I/O”
24
OPA363/OPA364 Application Specs
 SRmin (V/μs) = 2 π fVOP (1e-6)
 Minimum Slew Rate to track input sinewave (@<1% Distortion?)
 SRmin = 2∙ π ∙1kHz∙(4.87Vpp/2)∙(1e-6) = 0.015V/μs
 OPA363/OPA364 = 5V/μs
 Choose Op Amp SR > 2 X SRmin
 Gain Error
 AVCL = Aol/(1+Aolβ)
 Aol @1kHz = 80dB = 10000
 β = 1 for Unity Gain Follower
 AVCL= 10,000/(1+10000∙1) = 0.99990001




0.009999% Gain Error @ 1kHz
≈ 12 Bit (1/2 LSB Accuracy)
Calibrate gain error at system level
Many systems are more concerned about relative changes than absolute
 A/D Initial Reference Error (0.02% < Typical Range < 0.2%)
 Settling Time
 OPA363/OPA364: tS = 1.5μs to 0.01%, VS=+5V, G=+1, 4V Step
 A/D tSAMP = 1.88μs so this looks like a possible good candidate
 tS to 0.01% < tSAMP
25
OPA363/OPA364 Application Specs
(continued)
 THD+Noise


OPA363/OPA364:
 THD+N = 0.002%, G=1, RL=2kΩ, VS=5V, f=1kHz, VOUT = 1Vrms
16Bit desired 0.0011%
 Open Loop Output Resistance (RO)
 OPA363/OPA364: RO = 200Ω
 Output Current



OPA363/OPA364: IO+ = 40mA,VOUT = +/-0.75V, +/-VS = +/-2.5V
OPA363/OPA364: IO- = 40mA,VOUT = +/-0.5V, +/-VS = +/-2.5V
OPA363/OPA364: IO+ & IO-= 10mA,VOUT = +/-2.25V, +/-VS = +/-2.5V
26
Filter Application Specs
tSAMPL
-
RFLT
RSW
CSH
+
CFLT
 RSW = 100Ω (Not needed for Buffer & Filter Calculations)
 CSH = 50pF
 Worst case ΔV across CSH is VREF

VREF = +5V
 tSAMPL = 1.88μs
27
Filter Application Specs (cont)
 Charge Transfer Equation: Q = CV
 Charge required to charge CSH to VREF


QSH = CSHVREF
QSH = 50pF∙5V = 250pC
 IDEAL CFLT (What does CFLT have to be for 1/2 LSB droop on CFLT to
change CSH by VREF)




“Charge Bucket” to fill CSH with only a 38μV (1/2LSB) droop on CFLT
QFLT =QSH
QFLT = CFLT (38μV)
250pC = CFLT (38μV) → CFLT = 6.6μF
 IDEAL CFLT = 6.6μF



Not a good, small, cheap high frequency ceramic capacitor
Not practical for Op Amp to drive directly (stability, transient current)
Isolation resistor likely not large enough to help isolate Cload and still meet
necessary filter time constant
28
Filter Application Specs (cont)
 Partition the “Charge Bucket”


95% from CFLT
5% from Op Amp
 CFLT value required to provide QSH with <5% droop on CFLT



QFLT = QSH
QFLT = CFLT (0.05VREF)
250pC = CFLT (0.05∙5V) → CFLT = 1nF
 During tSAMPL the Op Amp must replace 5% VREF on CFLT

Ensure CFLT is at least 10X > CSH
 This implies dominant load for Op Amp Buffer is CFLT
 1nF = 20 X 50pF  CFLT = 20X CSH
29
Filter Application Specs (cont)
 Time required for CSH & RSW to settle to 1/2LSB @ 16 Bits




RSW = 100Ω (If unknown assume 100 Ω)
τA/D = RSW CSH = 100Ω∙50pF = 5ns
tA/D settle = 12 τA/D = 60ns
Small in comparison to tSAMPL
 RFLT Calculation

tFLT settle = tSAMPL = 12τFLT
 tFLT settle = 1.88μs = 12τFLT

12τFLT = 1.88μs → τFLT = 157ns

τFLT* = 0.60 τFLT
 40% Margin for:

Op Amp Output Load Transient

Op Amp Output Small Signal Settling Time

τFLT* = RFLT CFLT
 0.60∙157ns = RFLT 1nF → RFLT =94.2Ω
 Use RFLT = 100Ω
30
Filter Application Specs (cont)
 Op Amp Transient Output Drive to RFLT & CFLT

IOpk max = (5% VREF)/(RFLT) = 250mV/100Ω = 2.5mA
 OPA363/OPA364:
IO+ & IO- = 2.5mA,VOUT ≈ +/-2.428V, +/-VS = +/-2.5V
 VS = +5V Single Supply  VOUT = +4.928V

31
Op Amp + Filter Analysis – Small Signal
 Modified Aol due to RFLT & CFLT

 Stability Check


-
fZX = 1/[RFLTCFLT2π]
 fZX = 1/[100Ω∙1nF∙2π] = 1.6MHz
VOA
OPA363/
OPA364
fPX = 1/[(RO + RFLT)CFLT2π]
 fPX = 1/[(200Ω + 100Ω)1nF∙2π] = 530kHz

Vfb
+
RO
RFLT


VFLT
ADS8320
CFLT
1nF
At fcl = 3.2MHz “Rate-of-closure” is
20dB/decade  fZX cancels fPX before fcl
fPX and fZX are < decade apart
 Phase of pole will be cancelled by
phase of zero
 Buffer Closed Loop Gain Bandwidth

fcl = 3.2MHz
 VOA BW >2x fcl



VOA f-3db = fcl = 3.2MHz
VOA BW > 2*fcl = 2*3.2MHz = 6.4MHz
OPA364 BW = 7MHz
32
OP Amp + Filter Analysis – Small Signal (cont)
fPX
AVCL
Modified
Aol
fZX
fcl
3.2M
33
Log Scale Trick
Log Scale Trick (fP = ?):
100
1) Given: L = 1cm; D = 2cm
fP = ?
80
A (dB)
2) L/D = Log10(fP)
60
3) fP = Log10-1(L/D) = 10(L/D)
40
4) fP = 10(L/D) = 10(1cm/2cm) = 3.16
L
20
5) Adjust for the decade range
working within –
10Hz-100Hz decade  fP = 31.6Hz
D
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
6) L = Log10(fp’) X D
where fp’ = fp normalized to the
1-10 decade range –
fP = 31.6  fP’ = 3.16
34
OP Amp + Filter Analysis – Small Signal (cont)
Small Signal Transient Response
 Small Signal Rise Time (10% to 90%)

tr = 0.35 / fcl
 tr = 0.35 / 3.2MHz = 0.109µs = 109ns
 Small Signal Settling Time Constant

τsettle ss = 1/(2πfcl)
 τsettle SS = 1/(2π∙3.2MHz) = 49.7ns
 Small Signal Settling Time

tsettle ss = 12τ = (12)(49.7ns) = 596.4ns
 Small Signal Transient Response < 40% tSAMPL

ttran ss < 40 % tSAMPL




tr + tsettle SS < (0.40)(tSAMPL)
109ns + 596.4ns < (0.40)(1.8µs)
705.4ns ? < 720ns
Close enough to proceed
35
OP AMP + Filter Noise Analysis
 Op Amp + Filter



BW = 1.6MHz
Vnoise = (Op Amp Noise)[(Filter BW)(Single Pole Noise BW Ratio)]
Vnoise = [17nV/√Hz][√(1.6MHz∙1.57)] = 26.94μVrms
 White Noise Dominant with 1.6MHz BW

Resistor Noise = √(4KTRB)
 B = (Filter BW)(Single Pole Noise BW Ratio) = 1.6MHz∙1.57 = 2.5MHz
 KT = 4.11x10-21 @ 25°C

100Ω noise = √[4(4.11x10-21)(100 Ω)(2.5MHz)] = 2.03μVrms → Negligible
 A/D Noise




SNR A/D = 88dB
SNR A/D = 20 Log10 (VINrms/Vnoiserms)
VIN = 5VPP = 1.7675Vrms
A/D Vnoise = 70.365μVrms
 System SNR



SNR System = 20Log10 {[VINrms] / √[(ADC Vnoise)2 + (Vnoise)2]}
SNR System = 20Log10 {[(4.87Vpp/2)(0.707)] / √[(70.365 μVrms)2 + (26.94μVrms)2]}
SNR System = 87.18dB
 ENOB (ideal) = [SNR(dB) – 1.76] / 6.02

ENOB System = [87.18 -1.76] / 6.02 = 14.19
36
ADS8320 On Test System
ADS8320 Data Sheet:
SNR = 88dB
THD = -86dB
SINAD = 84dB
SFDR = 86dB
ENOB = 14.33
37
OPA364, Filter, ADS8320 On Test System
Op Amp+Filter+ADS8320
Calculated:
SNR = 87.18dB
ENOB = 14.19
38
Comparison of Tests
ADS8320 Only
OPA364, Filter, ADS8320
AD8S320 Data Sheet:
SNR = 88dB
THD = -86dB
SINAD = 84 DB
SFDR = 86dB
ENOB = 14.33
Op Amp+Filter+ADS8320
Calculated:
SNR = 87.18dB
ENOB = 14.19
39
Reference Buffer Selection
 Reference is DC, right? So a slow op amp is OK?
 No! Same thing happens on reference input as analog input, but
it must settle in 1 clock cycle!
 Requirements on reference buffer are even more stringent.
 Possible Circuit:
40
Promise of more to come…
 This is just the beginning
 Tuning for BEST results








Filter Capacitor
AC Magnitude
DC Offset
Sample Rate
Different converters
Testing DC parameters
Testing AC parameters
Rules of Thumb & Tricks

To Optimize Op Amp, Filter, A/D System
 Each Customer WILL NEED TO TEST His/Her Final Application
41
Selecting the Right Amplifier
for a
Precision CDAC SAR A/D
Summary of Procedure
42
Summary Steps - CDAC SAR A/D Input
Buffer & Filter Selection
Op Amp
Filter
A/D
+VCC
VOA
+VREF
VFLT
RSW
-
+
Aol x VDIFF
RO
RFLT
+
VIN
CSH
SWSAMPL
?
?
E
D
CFLT
?
DOUT
VREF
SWCONV
?
Frequency?
Amplitude?
A
C
B
43
Buffer / Filter Selection for CDAC SAR A/D Input
1) Specify System Voltages
2) Define maximum input signal
 Highest Frequency
 Largest Voltage Swing
3) Choose A/D Converter
 Select Number of Bits of Resolution
 Select Maximum Throughput Rate (Sampling
Rate)
 Select Minimum Acquisition Time (tSAMP)
 Use DCLOCK stop trick if longer tSAMP is desired
4) Choose CFILT
 VREF is max ΔV across CSH
 QSH = CSHVREF
 QFLT = QSH
 QFLT = CFLT(0.05VREF)
 Ensure CFLT is at least 10X > CSH
44
Buffer / Filter Selection for CDAC SAR A/D Input (cont.)
5) Choose RFILT
 tFLT settle = tSAMPL = (#τ)τFLT
(where #τ is number of time constants to reach 1/2LSB settle –
i.e. 12 time constants for settling to ½ LSB for 16Bit A/D)
 Solve for TFLT
 τFLT* = 0.60 τFLT
 τFLT* = RFLT CFLT  Solve for RFLT
6) Calculate Op Amp Transient Output Drive to RFLT & CFLT
 IOpk max = (5% VREF)/(RFLT)
7) Calculate Op Amp Unity Gain Bandwidth
 First pass select unloaded Op Amp UGBW > 2 X VFLT f-3db
 VFLT f-3db = 1/[RFLTCFLT2π]
45
Buffer / Filter Selection for CDAC SAR A/D Input (cont.)
8) Op Amp Selection - General
 Choose Buffer or Inverting Buffer Configuration
 If Buffer on Single Supply beware of “Input CMV
Crossover”
 Slew Rate: SRmin (V/μs) = 2πfVOP (1e-6)
 Choose Op Amp SR > 2 X SRmin
 Gain Error (at the maximum input signal frequency)
 AVCL = Aol/(1+Aolβ)
 A/D Initial Reference Error (0.02% < Typical Range < 0.2%)
 Settling Time
 tS to 0.01% < tSAMP
 THD+N
 Close to desired ½ LSB chosen Accuracy
 Op Amp Current Drive [IOpk max = (5% VREF)/(RFLT)]
 Choose for VOPK @ IOpk max
 Unity Gain BW:
 First pass select unloaded Op Amp BW > 4 X VFLT f-3db
 Output Resistance (RO)
 Factory Only Parameter (if not specified in data sheet)
46
Buffer / Filter Selection for CDAC SAR A/D Input (cont.)
9) Op Amp Selection – Small Signal
 Modify Aol due to RFLT & CFLT
 fPX = 1/[(RO + RFLT)CFLT2π]
 fZX = 1/[RFLTCFLT2π]
 Stability Check
 At fcl = 3.2MHz “Rate-of-closure” is 20dB/decade 
fZX cancels fPX before fcl
 fPX and fZX are < decade apart 
Phase of pole will be cancelled by phase of zero
 Buffer Closed Loop Gain Bandwidth = fcl (from modified Aol)
 VOA BW >2x VFLT BW
 VOA f-3db = fcl
 VFLT f-3db = 1/[RFLTCFLT2π]
 Small Signal Transient Response
 ttran ss < 40 % tSAMPL
 tr + tsettle SS < (0.40)(tSAMPL)
 τsettle ss = 1/(2πfcl)
 tsettle ss = (#τ) X τsettle SS
47
Buffer / Filter Selection for CDAC SAR A/D Input (cont.)
10) Op Amp + Filter Noise
 Vnoise = (Op Amp Noise)[(Filter BW)(Single Pole Noise BW Ratio)
 Single Pole Noise BW Ratio = 1.57
 White Noise Dominant at wide BW
 Resistor Noise = √(4KTRB)
 B = (Filter BW)(Single Pole Noise BW Ratio)  Negligible?
 KT = 4.11x10-21 @ 25°C
11) A/D Noise
 SNR A/D = 20 Log10 (VINrms/Vnoiserms)
 Calculate A/D Vnoise
12) System SNR
 SNR System = 20Log10 {[VINrms] / √[(ADC Vnoise)2 + (Vnoise)2]}
 Calculate SNR System
13) System ENOB = [SNR(dB) – 1.76] / 6.02
 Calculate System ENOB
14) Prototype & Test Final Configuration
48
Buffer Op Amp RO (Output Resistance)
Part
RO
(ohms)
Part
Ro
(ohms)
Part
Ro
(ohms)
OPA132
80
OPA348
600
OPA627
55
OPA227
40
OPA350
50
OPA684
50
OPA277
10
OPA353
44
THS4503
14
OPA300
20
OPA354
35
TLC080
100
OPA335
90
OPA355
40
TLC081
100
OPA336
250
OPA356
30
TLC2272
140
OPA340
80
OPA363
160
TLE2071
80
OPA343
80
OPA380
30
TLV2461
173
49
Appendix - Facts about RO and ROUT
An Analysis of an Op Amp’s
Open Loop Output Resistance
and
Closed Loop Output Resistance
50
Op Amp Model for Derivation of ROUT
RF
RI
RO
-IN
RDIFF
VFB
VE
xAol
+
VO
IOUT
-
1A
+
+IN
VOUT
Op Amp Model
ROUT = VOUT/IOUT
51
Derivation of ROUT (Closed Loop Output Resistance)
b = VFB/VOUT = [VOUT (RI / {RF + RI})]/VOUT = RI / (RF + RI)
ROUT = VOUT/IOUT
VO = -VE Aol
VE = VOUT [RI/(RF + RI)]
VOUT = VO + IOUTRO
VOUT = -VEAol + IOUTRO
VOUT = -VOUT [RI/(RF + RI)] Aol+ IOUTRO
VOUT + VOUT [RI/(RF + RI)] Aol = IOUTRO
VOUT = IOUTRO / {1+[RIAol/(RF+RI)]}
ROUT = VOUT/IOUT =[IOUTRO / {1+[RIAOL/(RF+RI)]}]/IOUT
ROUT = RO / (1+Aolb)
52
OPA353 Specifications
RO = 40Ω
ROUT (@1MHz, G=10) = 10Ω
Aol @1MHz = 29.54dB = x30
53
OPA353 ROUT Calculation
RF
9k
RI
1k
VOUT
-IN
RDIFF
VFB
xAol
VE
+
+IN
RO
0.1mV
x29.54dB
x30
+

1mV
- 4mV +
VO
-
+
3mV
IOUT
0.1mA
Op Amp Model
VOUT = IOUTRO / {1+[RIAol/(RF+RI)]}
RO = 40Ω
ROUT = VOUT/IOUT
ROUT (@1MHz, G=10) = 10Ω
ROUT = 1mV/0.1mA
ROUT = 10
Aol @10mHz = 29.54dB = x30
54
ROUT vs RO
 RO does not change when feedback is used to close the loop
 Closed loop feedback forces VO to increase/decrease
 The increase/decrease in VO appears at VOUT as a
reduction in RO
 ROUT is the net effect of RO and closed loop feedback
controlling VO
55
Op Amp Model for AC Stability Analysis
 RO is defined as the Op Amp’s Open Loop Output Resistance
 RO is measured at IOUT = 0 Amps, f = 1MHz (use the unloaded RO for
AC stability calculations since it will be the largest value which is the worst
case for AC stability analysis)
 RO is included when calculating bfor AC Stability Analysis
RF
10k
b= VFB / VO
VFB
RI
10k
R1
10k
-IN
R2
10k
RO
VOUT
RFILT
100
VFILT
RDIFF
VERR
100M
+
C1
1.59mF
X(1X106) -
X1
+
X1
C2
15.9pF
-
VO
+
200
CFILT
1nF
-
+IN
120dB
DC open loop gain
First Aol Pole
10Hz
Second Aol Pole
1MHz
Output
RO = 200
AC Small Signal Op Amp Model for Stability Analysis
56
Further Investigation of RO & ZO
For a detailed discussion of RO and ZO refer to:
http://www.analogzone.com/acqt0529.pdf
Operational Amplifier Stability –
Part 7 of 15: When Does RO Become ZO?
Bipolar Output Op Amp – Open Loop Output Impedance
 Resistive, RO, within unity gain bandwidth of op amp
CMOS RRO Op Amp – Open Loop Output Impedance
 Resistive, RO, at high frequencies
Our stability concerns for this technique are at high frequencies
 Capacitive, CO, at low frequencies
57
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58