Transcript The Construction Status of the ATLAS Silicon Microstrip Tracker

The Construction Status of the ATLAS Silicon
Microstrip Tracker
D. Ferrère on behalf of the SCT collaboration
DPNC, University of Geneva
 General Description
 Silicon Detectors
 Electronics
 Electrical Tests
 Module Assembly
 Summary & Status
Didier Ferrère, Geneva University
Como, October 2001
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Atlas at LHC
LHC will provide protons and ions collisions
Atlas
A designed luminosity of 1034 cm-2s-1
p-p collision with 14 TeV in the center of mass
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The Atlas Detector
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Physics Motivations
•Higgs in SM and in MSSM
•Supersymmetric Particles
•B physics (CP violation, ...)
•Exotic physics
Requires a good tracking performance:
Secondary vertices
Impact parameters resolution
Track isolation
Measurement of high momentum particles
Simulated Event in
the Inner Detector
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SCT Environment
23 overlapping interactions every bunch crossing
(at the full Luminosity)
A bunch-bunch crossing every 25ns (40MHz)
Maximum equivalent 1 MeV neutron fluence
after 10 years is ~ 2.1014 n/cm2
Operating temperature on silicon detectors is -7oC
to contain the reverse annealing and the leakage
current
Maintenance will likely require yearly warm-up
of 2 days at 20oC and 2 weeks at 17oC
Material < 0.4 X0 at the outer SCT envelope
Operation in a 2 Tesla solenoid field
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SCT in the Inner Detector
SCT:
•4 Barrels + 2x9 wheels
•4 different module types
in the wheels
• h < 2.5
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The SCT Semiconductor Tracker
Barrel diameters:
B3: 568 mm
B4: 710 mm
4088 Modules
B5: 854 mm
~ 61 m2 of silicon
B6: 996 mm
15,392 silicon wafers
~ 6.3 million of readout channels
5.6 m
1.04 m
9 wheels
1.53 m
4 barrels
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9 wheels
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The SCT module types
2112 Barrel modules
936 Outer Forward Modules
640 Middle Forward Modules (incl. 80 Short Middle)
400 Inner Forward Modules
Barrel
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Module Pictures
A Barrel Module
• 2 daisy chained detectors / side
• The Kapton hybrid is bridged
over the detectors
• The cooling pipe is on the connector
side
An Outer Forward Module
•2 daisy chained detectors / side
• The Kapton hybrid is at the far end
• The cooling area is common with
the mounting blocks
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1 Barrel detector type
5 Forward detector types:
Silicon Detector Pictures
Single sided p-in-n detectors
W12: Inner Module
768 strips
Size ~ 6x6 cm2
285 mm thick
W21 & W22: Middle Module
W31 & W32: Outer Module
Barrel Pitch : 80 mm
Forward Pitch:
•W31 and W32: 161.5 mrad
•W12, W21 & W22: 207 mrad
Scratch pads for identification – Corresponds to DB serial number
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Silicon Detector Status
The detectors passed the Production Readiness Review in August 2000. The
production delivery started this year.
The detector purchases is distributed as followed:
Manufacturers
Hamamatsu
(Japan)
CiS
(Germany)
Sintef*
(Norway)
Contribution
79%
17%
4%
Sensor types
All
Wedges
Barrels
* On going qualification
Detector Delivery in Geneva
Delivery status of Hamamatsu
detectors in Geneva University
Detector number
Total
180
160
140
120
100
80
60
40
20
0
W31
W32
Total ordered:
Delivered:
Rejected:
% delivered:
Mar-01
Apr-01
May01
Jun-01
Jul-01
2500
570
4
22.64
Aug-01
Month
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Silicon Detector – Some Specifications
Total leakage current at 20 oC: <6 mA@150V and <20 mA@350V
Leakage current stability: to increase by not more than 2 mA @150V in dry air over 24 hours
Depletion Voltage < 150V
R bias = 1.25 +/- 0.75 MW (Poly-silicon or implanted technology)
C coupling >= 20 pF/cm @ 1kHz
Pre-Irradiation
C interstrip < 1.1pF/cm @ 100kHz @ 150V bias
R interstrip >2x R bias at operating voltage
Strip metal resistance <15 W/cm
Strip quality: a mean of >99% good readout strips per delivery batch. Not less that 98% /detector
Total leakage current <250 mA up to 450V @ -18 oC
Post-Irradiation
Leakage Current stability:to vary by no more than 3% in 24 hours at 350V at -10 oC
Strip defects: Number of strip defects (dielectric & metal) within pre-irradiation acceptance level
Charge collection: Maximum operating voltage for >90% of maximum achievable charge : 350V
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Quality Control consists of systematic
checks for Visual Inspection and IV scan &
sub-sample tests (10% of the detectors):
Depletion voltage, full strip test, metal strip
resistance and Interstrip capacitance
Silicon Detector Quality Control
Up to now only few rejections has
been made based on visual defects
and extra currents.
nA
Example of W31 normalized current @ 20oC
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Silicon Detector Quality Control
W31 - Defect strips
Open, Short, bias resistor break, pin
hole, oxide punch through, implant
break.
0.082 % of detective strips out of 172 detectors
# of detectors
The defective strips are identified by
Hamamatsu and the QC at the
Institutes. The full strip test allows to
identify all possible defects like:
140
120
100
80
60
40
20
0
10
8
6
4
2
0
0
0
2
4
2
4
6
6
8
8
10
10
12
12
14
14
# of bad channels
W32 - Defect strips
LCR meter allows to measure coupling
capacitance and the relative bias
resistor.
0.044 % of detective strips out of 170 detectors
# of detectors
The detectors are slightly biased during
the measurement and up to 100V DC is
put on the strips.
160
140
120
100
80
60
40
20
0
10
8
6
4
2
0
-1
0
2
4
4
6
9
8
10
14
12
14
# of bad channels
Hamamatsu series production delivered in Geneva
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Silicon Detector – Irradiation
The detectors are irradiated using 24 GeV protons at CERN PS.
All strips are grounded and the backplane is biased to 100V during the irradiation.
mA
Typical annealing is done at the minimum of the beneficial and reverse annealing.
V
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Silicon Detector – Charge Collection after Irradiation
The detectors were annealed 7 days at 25oC
after an irradiation of 3x1014 p/cm2
Barrel
The readout was made with SCT 128A
chips (DMILL technology). A Ru106 source
was used for the injected charge.
W31
350V
The measurement was taken at –18oC
A S/N plateau around 17:1 is
reached above 350V for all the
Hamamatsu detectors
D. Robinson
The Signal to noise ratio is for a strip
length of ~6 cm
W32
Similar results are obtained for the
other detector purchases
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Binary ABCD chips are based on
DMILL BiCMOS technology
•Noise with detectors (12 cm strips): < 1500 e•Efficiency: 99%
The Front End Electronics
•Pipeline Length: 3.2 ms (128 locations)
•Functionality temperature range: -15 to 30oC
•Occupancy due to Noise : 5x10-4
•Double pulse resolution: 50ns for 3.5fC following
3.5 fC signal
•Power dissipation: < 3.8 mW/channel
•Specified total radiation dose:
2x1014 n/cm2
10 Mrad
•Shaping time ~ 20 ns
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ABCD 3T – Trimming function
The Front End Electronics
The readout chips passed the PRR in July 2001.
Pre-series have started with 35 wafers already delivered. In November 200 wafers
are expected. The measured yield on the pre-series is spread from 10 to 50 % and
the expected yield in average is ~26%. ATMEL think they can improve it!
Yield consideration based on:
• All analog and digital functionalities are OK
(tested with threshold, bias and frequency scan)
• No Icc or Idd problem
• No bad channels
The wafer screening for the Quality
Control will be done at 3 places:
CERN, RAL and SCIPP.
Current testing time ~9 hours/wafer
Will be decrease during prod by a factor 2
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The Module Test Set-up
SCTLV:
Conventional Cable (30m)
Low Voltage
power supply,
merges with HV
PPB2
Thick
power
tapes
(~4m)
ATLAS-SCT
Detector Module
SCTHV:
High Voltage
power supply
Tests on modules:
~25m optical
fibres
PPB1
The SCT DAQ (software and hardware) readout
test set-up is the same in all the laboratories.
OPTIF:
Thin
power
tapes
(~1.5m)
Bi-phase Mark
Encoding + optical
data receiver
MUSTARD:
Receives and
decodes data
Opto-harness
SLOG:
Generates slow
commands, merges
with fast commands
Temperature and
Humidity Probes
CLOAC
FANOUT
CLOAC:
Generates master
clock, trigger and
reset
National
Instruments
PC-VME
Interface
• Measured gain curve (with internal calibration
signal)
• Hit occupancy versus comparator threshold
without signal (“Noise Occupancy”)
• Determination of ENC (from response curve
and Noise Occupancy)
•Pulse shape through variation of calibration
pulse delay
• Power consumption at different settings
• Various digital function checks (pipeline &
data transfer)
VME
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Signal and ENC determination
“S-curves”:
• Measure hit
occupancy as a
function of the
threshold
• Fit error function to
occupancy “S-curve”
• Determines mean
signal & rms
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Module Performances
Pre-irradition
• ENC noise: 1400-1500e• NO @1fC: 1-2 x 10-5
Post-irradition
5x10-4
• ENC noise: 1900e• NO @1fC: 2-3 x 10-4
*
* Acceptance criteria : 5x10-4
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KEK Test Beam – Median Charge
Preliminary results from N. Unno
A small difference
between barrel and endcap modules is observed
and could be due to:
Larger effective pitch for
the forward and less
charge sharing.
(V)
Barrel and End-cap modules are functioning
well and are very similar
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KEK Test Beam – Efficiency and Noise Occupancy
Preliminary results from N. Unno
Specs
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Test Beam Results – Spatial Resolution
Spatial resolution in strip
coodinate (+/- 20mrad
stereo angle)
 23mm
 compatible with digital
resolution for 80mm pitch
Gives spatial resolution in
X/Y
• s(X) = 20mm
• s(Y) = 750mm
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Multiple Modules in the System Test
 Determine performance of individual modules
 Measure noise and “inter-module” effects
 Optimize grounding and shielding in realistic
setup
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Noise Performance in the System Test
Tests on multi-modules barrel setup
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Noise Comparison System Test versus Single Module Test
ENC System Test ENC Individual Module ENC Noise Occupancy
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Barrel alignment system
Module Assembly
Aligned forward detector pairs onto transfer plates
Parallel module production will take place
Barrel: KEK, RAL, LBL, Oslo – Starting at the end of this year
Forward: Freiburg, Geneva, Melbourne, Nikhef, MPI, UK-North, Valencia
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Module Mechanical Tolerances
SCT Philosophy: Build modules to a sufficiently high tolerance that alignment
corrections “within the module” are not needed for track reconstruction
Physics requirement: Alignment accuracy rms (in micron)
Direction (cyl. Coord.)
Barrel
Forward
R
100
50
f
12
12
z
50
200
Internal module build tolerances: Alignment tolerance (in micron)
Barrel
Forward
XY wafer to wafer plane in 1 plane
4
4
XY back to front plane
8
8
XY relative to mounting holes
30
20
Z surface of silicon detectors
40
100
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Engineering
Barrel sector close-up view of
brackets, pipes, modules…
Forward disc sector
Middle cooling circuits, cooling
blocks and low mass tapes
Barrel support structure is
under construction
Forward support structure is
ready for FDR
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Summary and Status
 Detectors
• The series production started beginning of 2001 and is well on the way
• ~ 36% of the detectors are delivered and the quality is very good
 Chips
• ABCD3T passed production readiness review and first lot of production wafers
are expected soon
 Modules
• Barrel modules passed FDR and will start production at the end of the year
• Forward modules require 1 more round of hybrid production before going to FDR
 Engineering, Off-detector Components, power distribution
• A series of FDRs started in spring
• First parts are/will be soon order for production
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Appendix - Typical Power Consumption
Module current and power
Before Irradiation
After Irradiation
Idd (mA)
550
750
Vdd (V)
4.0
4
Icc (mA)
950
560
Vcc (V)
3.5
3.5
Power (W)
5.2
5
ICC  after irradiation due to the optimization of the FE setting:
• before irr: Ipre = 220 mA and Ishap = 30 mA
• after irr: Ipre = 150 mA and Ishap = 24 mA
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Appendix – Prototype Components of the Forward Modules
Spine
Kapton Hybrid
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Appendix – Optical Links
Opto-packages on the dog-leg (Barrel)
Forward Opto-plug-in:
PIN receiver (Clock & Control BPM) &
2 VCSEL lasers for data links
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Appendix – Forward Electrical Performances
From G.Moorhead
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Appendix – Forward Electrical Performances
From G.Moorhead
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Appendix – Thermal Simulation
 Requirement: Prevent Thermal Runaway
 Facts of life:
 Leakage current (4 detectors of the module) after 10 years in the LHC reaches
~2mA @ 500V @ -10  C (spec: <1. 0mA @450V @- 18  C)
 Increased ASIC power estimates: now 6.8W per module
 ASICs are close to detector and module designs are optimized to limit heat
transfer to detectors.
 Some thermal design features:
 Baseboard or spine are made of TPG (Thermo Pyrolitic Graphite).
Conductivity: 1700 W/ m/ K along length
 Improved hybrid substrate (metallised CF or CC) reduces hybrid & ASIC
temperatures, reducing convection (~ 0.5W with CF)
 Evaporative C3F8 cooling - extensive system prototyping has been done.
It looks promising using -20  C at the cooling block
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Appendix – Thermal Simulation
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Module Power Consumption
After annealing
@ 40MHz
(10 days continuous warm operation)
1400
Idd [mA]
1200
1000
800
600
400
Idd(B037 mA)
200
Idd(B017 mA)
Idd(B020 mA)
0
0
20
40
60
clk [MHz]
• observed on some modules increase of Idd current (up to x2 normal current) but still
within specs for current and total module power (6.8W/module)
• on effected module current comes from all chips uniformly
• under investigation ...
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