Transcript EE362L, Fall 2006 Isolated Firing Circuit for H

EE462L, Spring 2014
Isolated Firing Circuit for
H-Bridge Inverter
(partially pre-Fall 2009 approach)
1
!
Isolation is needed because we have three separate
MOSFET source nodes, and these three nodes are
ground references for the respective firing circuits
Vdc
(source of power delivered to load)
A+
One logic
signal
toggles
A+,A–
Local ground
reference for A+
firing circuit
Local ground
reference for B+
firing circuit
S
S
S
Load
A–
Local ground
reference for A−
firing circuit
B+
B–
S
One logic
signal
toggles
B+,B–
Local ground
reference for B−
firing circuit
2
Output of the Comparator Chip
Comparator Gives V(A+,A–)
wrt. Common (0V)
V(A+,A–)
+12V
from DC-DC chip
1.5kΩ
+12V
1.5kΩ
–12V
270kΩ
Vtri
8
1
Vcont > Vtri
Comp
5
1kΩ
Vcont
4
Vcont < Vtri
Since the comparator
compares signals that can be
either positive or negative, the
comparator must be powered
by ±V supply
Use V(A+,A–) wrt. –12V
270kΩ
Vcont > Vtri
–Vcont
+24V
–12V
from DC-DC chip
0V
Common (0V) from DC-DC chip
Vcont < Vtri
3
Comparator Gives V(B+,B–)
wrt. Common (0V)
Output of the Comparator Chip
V(B+,B–)
+12V
from DC-DC chip
–Vcont > Vtri
+12V
1.5kΩ
–12V
1.5kΩ
270kΩ
Vtri
8
1
Comp
5
1kΩ
Vcont
4
Since the comparator
compares signals that
can be either positive or
negative, the
comparator must be
powered by ±V supply
Use V(B+,B–) wrt. –12V
270kΩ
–Vcont
– Vcont < Vtri
–12V
from DC-DC chip
Common (0V) from DC-DC chip
– Vcont > Vtri
+24V
0V
– Vcont < Vtri
4
The control signals at the open-circuited output
of the PWM control circuit are +24V, or 0V
When V(A+,A−) is 24V,
MOSFET A+ is on,
MOSFET A− is off
When V(A+,A−) is 0V,
MOSFET A+ is off,
MOSFET A− is on
V(A+,A−)
control
signal
V(B+,B−)
control
signal
MOSFETs B+ and B− work
the same way with V(B+,B−)
Reference (is −12V
from DC-DC chip)
DC
wall
wart
AC wall wart
(marked with yellow paint)
5
+24V
0V
+24V
Look for symmetry of
pulse centers
0V
Save screen
snapshot #3
Figure 13. Output control voltage V(A+,A–) on top, and V(B+,B–) on bottom, with respect
to protoboard –12V reference, with ma > 0 (the situation shown is where Vcont is positive)
+24V
0V
+24V
Look for symmetry of
pulse centers
0V
Figure 14. Output control voltage V(A+,A–) on top, and V(B+,B–) on bottom, with respect
to protoboard –12V reference, with ma > 0 (the situation shown is where Vcont is negative)
6
Once the MOSFET is
connected, this
asymmetrical circuit will
add blanking by making
the turn-on slower than
the turn-off. (blanking is
the opposite of overlap)
Wait until
next week
One firing circuit for each MOSFET, with each firing
circuit mounted on a separate protoboard. Protoboards
A– and B – can share a power supply and ground . A +
and B + must each use separate power supplies
and
grounds. Do not connect any of these grounds to the
ground of the control circuit.
MOSFET
G
D
S
100kΩ
Switching diode
Overlap is the time that
A+ and A− are
simultaneously “on,”
which should be avoided.
Hence, some blanking
(time between one
turning off and the other
turning on) is desirable.
10Ω
1.2kΩ
green
Grounds (isolated
from control circuit)
0.1µF
blue
5
4
green
Driver
8
A+ and B+ use inverting drivers
(1426’s). A– and B– use non inverting drivers (1427’s) . The
optocouplers provide an additional
inversion.
1
blue
red
green
5
10kΩ
4
Opto
8
1
Optocoupler is currentcontrolled. Gate current
Isolating
turns on the transistor,
barrier
which pulls down the
Powered by +12V that is isolated from the
collector voltage.
PWM control circuit
Outline of
protoboard
blue
blue for A+,B+,
violet for A–,B–
14mA
O+ O–
(see Figure 2 for connections)
7
14mA to Opto Input Yields ≈ 0V to Input of Driver Chip,
so Inverting Driver Chip Turns MOSFET ON
Isolating
barrier
!
Spec. sheet current transfer ratio
 0.2 to 0.3 (times 14mA)
+12V
1.2mA (will pull down Vdriver to zero)
14mA from
control circuit
10kΩ
+
To
driver
Vdriver = 0V
–
8
0mA to Opto Input Yields 12V to Input of Driver Chip, so
Inverting Driver Chip Turns MOSFET OFF
!
Isolating
barrier
+12V
0mA
0mA from
control circuit
10kΩ
+
Vdriver = 12V
–
To
driver
9
We use the control signals to send 14ma through
optocouplers on each of the four firing circuit boards
A+
Firing
A+ and A− are
daisy chained
8”
A–
Firing
O+ O–
B+
Firing
O+ O–
O+ O–
O+ O–
blue
blue
violet
blue
Jack for
DC wall
wart
B–
Firing
Individual protoboard for
each firing circuit
violet
–12Vdc
regulated
V(A+,A–) V(B+,B–)
Control Circuit from Previous Lab
Optically-isolated firing
circuits. Mount drivers
near the MOSFETs
Jack for
AC wall
wart
B+ and B− are
daisy chained
(for complementary
outputs)
Figure 2. Physical layout of firing circuits
(A+ opto and driver are powered by a +12V isolated DC converter chip. Likewise, B+ is powered
by another +12V isolated DC converter chip. A– and B– are powered by the DC wall wart.)
So, each 14mA control signal passes through two optocouplers in series
10
With 14mA, the LED of each optocoupler has about 1.6V drop
• 24V control signals from the comparators, less 3.2V drop across two
series optocoupler LEDs, and with 14mA, requires about 1.5kΩ of
resistance in series with the daisy-chained optocouplers
• If applied half the time, 24V across a 1.5kΩ resistor would produce
about 0.2W. So, it is a good idea to size up to ½W resistors.
11
Thus, you use ½W series resistors between the
comparator chip and the output terminals
500Ω
trimmer
V(A+,A–) V(B+,B–)
+12Vdc regulated from 2W,
DC converter chip
These ½W resistors can get hot - keep them off
the surface of the protoboard
1.5kΩ, ½W
red
1kΩ
High-pass filter to
block DC
red
red
100kΩ
0.01µF
1kΩ
1.5kΩ, ½W
Filtered and
buffered
triangle wave
blue
270kΩ
Vcont
blue
7
1
Waveform Gen.
blue
8
0.01µF
(freq. control)
2Vdc
ated from
W, DC
erter chip
14
8
Approx
22kHz
triangle
wave
5
Op Amp
1
8
green
5
1kΩ
Comp
4
1
4
violet
10kΩ
9.53kΩ
The IC is upside
down to minimize
wiring clutter
–Vcont
1kΩ
trimmer
270kΩ
1kΩ
blue
blue
Vcont
green
violet
violet
violet
Protoboard common connected to 0V output pin
12
Layout of inverter control circuit and isolated firing circuits
No MOSFETs connected yet (i.e., the drivers are open-circuited)
A+
A−
B+
B−
DC
wall
wart
AC wall wart
(marked with yellow paint)
13
DC converter chip
feeds A+ circuit
• Keep the 0.1µF capacitors
across the drivers to prevent
driver failure
ground rail fed by wall wart
Non-inverting driver
for A– (1427’s)
12V rail fed by wall wart
12V rail fed by DC converter chip
Inverting driver
for A+ (1426’s)
ground rail fed by 0V output pin of DC converter chip
Zoom-in view of A+ and
A– isolated firing circuits
• Use the same pattern for B+
and B–
• One DC converter chip feeds
A+
• Another DC converter chip
feeds B+
• Wall wart feeds A− and B−
Wall wart feeds A– circuit
14
Side view of A+ and A– isolated firing circuit and single 12V
isolated DC-DC converter chip that powers A+
−
+
wall
wart
input
−
+
chip
output
Socket each single DC-DC converter chip,
using one half of an 8-pin SIP socket.
Carefully break an 8-pin SIP socket in
half. Do this by clamping on one-half
with your long-nose pliers, and then
bending the other half down with your
fingers. It should be a clean break.
15
!
Input and Output Voltages of Optocoupler
Vcont = 0 (i.e., ma = 0) in this Snapshot
Look for Symmetry Among all Four Circuits
Opto Input (the 1.5kΩ resistor drops the voltage
from 24V to 3.2V)
3.2V
V(A+,A–)
0.5V
Phototransistor
turning on
12V
Opto A +
output
Phototransistor
turning off
As expected, the opto
output is inverted
0V
Save screen
snapshot #1
This phototransistor turn off delay will limit
your PWM operating frequency
Different time-constants to avoid shoot-through
(i.e. to provide a “dead-time”)
16
Look for Nearly Perfect Alignment Between V(A+,A−) Signal to
Optocoupler, and Output of A+ Inverting Driver Chip
V(A+,A–)
In
phase
A+ driver
output
17
Look for Nearly Perfect Out of Phase Alignment Between V(A+,A−)
Signal to Optocoupler, and Output of A− Non-Inverting Driver Chip
V(A+,A–)
Out of
phase
A– driver
output
18
Now the present circuit based on PCBs:
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Key new component: IRS21844
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IRS21844
High output
Low output
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Actual pinout
IRS21844
Blanking time and isolation already integrated in a single IC
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