Transcript ECE 352 Electronics II

Ch 10 MOSFETs and MOS Digital Circuits
* Examine MOSFET use in inverters
* Inverter = two transistors in series
 Input to gate of driver (at least)
 Second transistor acts as load
 Output off connection between
transistors
* NMOS Inverters
 Enhancement driver, resistor load
 Enhancement driver and load
 Enhancement driver, depletion load
* CMOS Inverter
 N channel driver, P channel load
Load
Driver
Vo
Vi
ECES 352 Winter 2007
* Analyze to find inverter performance:
* Voltage transfer characteristic
*
Noise margins
*
Power dissipation
*
Switching speed
Ch 10 MOS Digital
1
MOSFETs and MOS Digital Circuits
* Inverters combined in series
and parallel to form digital
circuits such as AND’s,
NAND’s, OR’s, NOR’s, flipflops, etc.
* Understanding inverter
operation is basic to
understanding and describing
digital circuit operation
* Also important in modifying
their design to enhance their
performance, e.g. speed,
power dissipation,
susceptibility to noise, and
fan-out capability
ECES 352 Winter 2007
Ch 10 MOS Digital
2
N-Channel Enhancement MOSFET
* Positive voltage on gate attracts
electrons to surface to form
“induced channel of electrons”.
* Channel forms path for electron
flow between source and drain.
* Without channel, have back-to-back
diodes in series between source and
drain so negligibly small current
ECES 352 Winter 2007
Ch 10 MOS Digital
3
N-Channel Enhancement MOSFET
* Basics of device operation




iDS
Saturation mode operation
(large VDS)
VTh = threshold voltage
No channel of electrons for
vGS < VTh
No current for vGS < VTh
VTh > 0 for enhancement
mode n-channel MOSFET
iDS
Channel formation
for vGS > VTh
Increasing vGS
Increasing vGS
VTh
ECES 352 Winter 2007
vDS
vGS
Ch 10 MOS Digital
4
N-Channel Enhancement MOSFET
iDS
vDS sat = v GS – VTh
Constant vGS
curve
ECES 352 Winter 2007
Ch 10 MOS Digital
vDS
5
N-Channel Enhancement MOSFET
* Cutoff region (vGS < VTh)
iDS
iD  0
* Triode region (vDS < vDSsat)
2


i

K
[
2
v

V
v

v
]
D
GS
Th
DS
DS
* Triode-saturation boundary at
vDS = vDSsat = vGS - VTh OR
where vGS - vDS = VTh
* Saturation region (vDS > vDSsat)
vDS sat = v GS – VTh
vGS
2
iDK

V
Th
where
K
1
W
nCox
2
L
Cox 
vDS
ox
tox
n  electron
mobility
in thechannel
incm2 /V sec
vn
electronelocity
v

E electric
fieldstrength
W  widthof thechannel
(perpendic
ular to
current
flow)
L  lengthof thechannel
(alongthecurrent
flow)

ECES 352 Winter 2007
Ch 10 MOS Digital
6
N-Channel Depletion MOSFET
* Basics of device operation

N-type
channel



Saturation mode
operation

iDS

VTh < 0 for depletion mode
n-channel MOSFET
VTh = threshold voltage
Channel exists even when no
bias is applied to the gate,
i.e for vGS = 0.
Drain current can flow for
vGS = 0 and for any vGS > VTh.
No channel of electrons for
vGS < VTh
No drain current for vGS < VTh
vGS
VTh
ECES 352 Winter 2007
Ch 10 MOS Digital
7
N-Channel Depletion MOSFET
iDS
* Cutoff region (vGS < VTh)
iD  0
* Triode region (vDS < vDSsat)
2


i

K
[
2
v

V
v

v
]
D
GS
Th
DS
DS
* Triode-saturation boundary at
vDS = vDSsat = vGS - VTh OR
where vGS - vDS = VTh
* Saturation region (vDS > vDSsat)
vDS sat = v GS – VTh
vGS
2
iDK

V
Th
vGS= 0
1
W
K nCox
2
L

Cutoff
vDS
* Only difference from enhancement mode
device is that the gate voltage may be
negative. But vGS must still be larger
than the threshold voltage for the device
to be on!
ECES 352 Winter 2007
Cox ox
tox
2
n electron
mobility
in the
channel
incm
/Vsec
v
electron
elocity
v
 n
E electric
field
strength
Wwidth
ofthe
channel
(perpendic
ular current
to flow
Llength
ofthe
channel
(along
the
current
flow)
Ch 10 MOS Digital
8
N-Channel Enhancement vs Depletion MOSFET
Enhancement MOSFET (VTh > 0 )
* Cutoff region (vGS < VTh)
iD  0
iDS
* Triode region (vDS < vDSsat)
2


i

K
[
2
v

V
v

v
]
D
GS
Th
DS
DS
vDS
* Triode-saturation boundary at
vDS = vDSsat = vGS - VThOR
where vGS - vDS = VTh
* Saturation region (vDS > vDSsat)
2
vGS

iDK

V
Th
vGS < VTh
iDS
Depletion MOSFET (VTh < 0 )
1
W
K nCox
2
L

Cox ox
tox
2
n electron
mobility
in the
channel
incm
/Vsec
v
electron
elocity
v
 n
E electric
field
strength
Wwidth
ofthe
channel
(perpendic
ular current
to flow
Llength
ofthe
channel
(along
the
current
flow)
vGS = 0
vDS
ECES 352 Winter 2007
Ch 10 MOS Digital
9
NMOS Inverter (E-MOSFET + Resistor Load)
* Analyze to find inverter
performance: voltage transfer
characteristic, noise margins, power
dissipation and switching speed
* Transistor characteristics (driver)
VDD5 V
RD 2K
+
+
vi
_
vo
_
VTh  1.0 V (enhancement mode)
Channel width W  5m, Channel length L  1m
Electron mobility  n  700 cm 2 / V sec
Gate oxide thicknes s tox  20 nm  2 x10  6 cm
Gate oxide capacitance
Cox   ox / tox
Cox  (3.9 x8.85 x10 14 F / cm) /( 2 x10  6 cm)
 1.77 x10  7 F / cm 2
1
W
 nCox
2
L
1
5 m
 (700 cm 2 / V sec)(1.77 x10  7 F / cm 2 )(
)
2
1m
K
 0.3 mA / V 2
ECES 352 Winter 2007
Ch 10 MOS Digital
10
NMOS Inverter - Load Line
* Device operation in inverter
VDD5 V
V
1.0V
Th
RD 2K
K0.3mA
/V2

Load line comes from connections of
transistor in the circuit
v
V
R
v
o
DD
Di
D
DSor
V v
iD DD
DS
R
R
D
D
+
vo = v DS

_
iDS

VDD/RD
=5V/2K
=2.5 mA
D


Increasing vGS
Load line
C
.
A
vDS

For a given vGS, e.g. 3V (=VTh+2V),
transistor’s operating point is where
load line crosses vGS = 3V transistor
characteristic.
Transistor must operate on load line
as gate voltage changes.
At points A, the transistor is in
cutoff mode (small vGS).
Between points A and C (larger vGS),
transistor is in saturation mode.
Between points C and D (even larger
vGS), transistor is in triode mode.
VDD
ECES 352 Winter 2007
Ch 10 MOS Digital
11
NMOS Inverter (E-MOSFET + Resistor Load)
VDD5 V
V
1.0V
Th
RD 2K
K0.3mA
/V2
* Voltage transfer characteristic
 Vo versus Vi
* Region I (A to B)
 0 < Vi < VTh
 iD = 0 since transistor is
off, i.e. in cutoff.
+
+
vi
vo
_
_
vo
iDS
5V
A
B
I
A to B
.
vDS
0
0
ECES 352 Winter 2007
VTh=1V
Ch 10 MOS Digital
5V
12
vi
NMOS Inverter (E-MOSFET + Resistor Load)
* Region II (B to C)
VDD5 V
V
1.0V
Th

RD 2K
K0.3mA
/V2


+
+
vi
Vi > VTh and iD > 0 since transistor is on.
iD is increasing as Vi = vGS increases
Transistor is operating in saturation
mode since vDS > vDSsat
vGSV
20.3mA
v1
2iR
iDK
V
Th
2 i
V
 mA
2
v
V
R
iR5
V2
K
0
.3 2v
1
V
o
DD
D
i


 V

vo
_
_
2


v
1
V
i
5
V0
.6
V
vo
iDS
vDSsat
5V
A
B
I
C
.
A to B
C
vDS
0
0
ECES 352 Winter 2007
II
VTh =1V
Ch 10 MOS Digital
5V
13
vi
NMOS Inverter (E-MOSFET + Resistor Load)
*
VDD5 V
V
1.0V
Th
RD 2K
K0.3mA
/V
vo vDSvDSsat
vGSVThvi VTh
+
+
vi
*
2
Where is point C and what are the corresponding
values of Vi and Vo?
At C, transistor is operating at the edge of the
saturation mode where
vo
_
_
Socombining
with
Load
Line
equation
vo VDDRDiR VDDKvi VTh RD weget
2
vi VThVDDKvi VTh RD
2
Solving
forvi we
get
-1 14KR
VDD 1 14(0.3mA
/V)2K(5V)
D
v


i(at C)
2KR
2(0.3mA
/V)2K
D
13.6

2.2V or 3.8V(not
possible
) and
sovi(at C)
2.2V
1.2
Then
v0(at C)
vi(at C)
VTh2.2V1.0V1.2V
iDS
vo
A
5V
C
.
ECES 352 Winter 2007
B
I
A to B
vDS
1.2V
0
II
C
0
VTh 2.2V
Ch 10 MOS Digital
14
5V
vi
NMOS Inverter (E-MOSFET + Resistor Load)
V
1.0V
Th
VDD5 V
*
K0.3mA
/V2
RD 2K
2
vDSvDS
vovo2] and
iDK
[2vGSV
]K
[2vi V
Th
Th
V v
iDiR DD o socombining
and
rearrangin
g we
get
R
D
+
+
vi
Region III (C to D)
 Vi > VTh and iD > 0 since transistor is still on.
 Transistor is operating in triode mode so
vo
_


2
 1VDD0
Kv
vo2Kvi V
o
Th
R
D R
D

_
1/2
2




1
4KV



DD
1


2
K
v

V




i
Th




2
K
v

V

i
Th

 
R
R

D
D

R
D 

vo 

2K
2K
iDS
vo
B
A
5V
D
I
C
II
A to B
.
vDS
C
1.2V
0.95V
0
ECES 352 Winter 2007
III
VTh
Ch 10 MOS Digital
At D, vi = 5V and
vo= 0.95V or
8.7V (not possible).
D
2.2V
15
5V
vi
Noise Margins for NMOS Inverter
(E-MOSFET + Resistor Load)
* Noise margin for low state

high
high
low

vo

VOH = 5V
NML= VIL - VOL
= 1.0 V- 0.95 V = 0.05 V
VOL=
0.95V
Vi =VOL
= 0.95V

VIL=VTh
= 1.0V
5V
vi

Input signal size with noise
that causes problems..
Normal low input signal size without noise.
ECES 352 Winter 2007
Ch 10 MOS Digital
Measures degree of
inverter sensitivity to noise
for the low state, i.e. how
large an input noise signal
causes problems at output.
Assumes identical inverter
providing input signal
Noise Margin =
NML = VIL - VOL where
 VOL = output voltage
when input set to VOH
 VIL = maximum input
voltage recognized as
a low input
For this inverter design,
NML is very low (0.05V) !
Can change by changing R
or VTh or transistor’s K.
16
Noise Margins for NMOS Inverter
(E-MOSFET + Resistor Load)
* Noise margin for high state

low
low
high

vo
VOH = 5V

NMH = VOH - VIH
Slope
= -1
VOL= 0.95V
5V
Input signal size with noise
that causes problems.
V
IH
Normal high input signal size without noise.
ECES 352 Winter 2007
vi

Measures degree of
inverter sensitivity to noise
for the high state, i.e. how
large a negative input
noise signal causes problems
at the output.
Assumes identical inverter
providing input signal
Noise Margin =
NMH = VOH - VIH where
 VOH = output high
voltage when input set
to VOL
 VIH = minimum input
voltage recognized as
a high input
Can change by changing R
or VTh or transistor’s K.
Vi=VOH

Ch 10 MOS Digital
How do we find VIH?
17
Noise Margins for NMOS Inverter
(E-MOSFET + Resistor Load)
* Noise margin for high state

low
low
high
vo

VOH = 5V
NMH = VOH - VIH
= 5 V- 1.83 V
= 3.17 V
Slope
= -1
Noise Margin = NMH = VOH - VIH
where
 VOH = output high voltage
when input set to VOL
 VIH = minimum input voltage
recognized as a high input
Can find VIH by using expression
derived for region II
vo VDDRDiR VDDRDKvi VTh2
dv
0
2RDKvi VTh1 so
dv
i
1
vi VIH VTh
2RDK
VOL=
0.95V
1
1V
1.83
V
2(2K)(0.3mA
/V)
C
2.2V
5V
VIH
II
ECES 352 Winter 2007
III
Vi=VOH
vi 
This VIH is less than 2.2V where
FET enters region III, so our
guess that device at VIH is in
region II is okay.
Ch 10 MOS Digital
18
Noise Margins for NMOS Inverter
(E-MOSFET + Resistor Load)
* Alternate analysis for Noise margin
for high state

low
low

high
Noise Margin = NMH = VOH - VIH
Can find VIH by using expression
derived for region III


2
vi VTh 1 VDD0
Kv
o v
o2K
RD RD

vo
Ifwepick
vo 1V, wegetforvi
VOH = 5V
1 5

0.3(1)2 2(0.3)(vi 1)  0
2 2

sovi 4.5VVIH
NMH = VOH - VIH
= 5 V- 4.5 V
= 0.5 V

VO= 1.0 V
C
VOL= 0.95V
2.2V
5V
VIH
II
ECES 352 Winter 2007
III
vi
The noise margin for the high state
NMH now becomes smaller.
 NMH = VOH – VIH = 5 V- 4.5 V = 0.5 V
 This is smaller than the previously
determined value, but is still a
factor of ten larger than that for
the low state NML = 0.05 V.
VOH
Ch 10 MOS Digital
19
Power Dissipation for NMOS Inverter
(E-MOSFET + Resistor Load)
*
V
1.0V
Th
VDD5 V
K0.3mA
/V2
RD 2K
*
Input low, output high.
 Transistor is off, iD = 0.
 Power dissipation PH = 0
Input high (5 V), output low (0.95 V).
vovDS
(D
)0.95
V
5V0.95
V
iD
2.0mA
2K
P
(2.0mA
)10
mW
L5V
+
+
vi
vo
_
*
_
Average Static Power Dissipation P
10
mW
1


P

P

P


5
mW
HL
2
2
iDS
vo
A
B
5V
D
C
.
I
A to B
vDS
III
C
1.2V
0.95V
0
ECES 352 Winter 2007
II
VTh
Ch 10 MOS Digital
D
2.2V
20
5V
vi
Propagation Delays and Switching Times
for NMOS Inverters
+
+
vi
_
vo
_
vi
t
vo
ECES 352 Winter 2007
* Previously considered static
characteristics of inverters, e.g.
Voltage transfer characteristic.
* Switching performance is also
of interest.
* Finite switching times are due
to the capacitance load on the
output and RC charging and
discharging times.
* Capacitance load comes from:
1) gate capacitance of
subsequent inverters to which
the output is connected and
2) capacitance of interconnect
wires to inputs of other gates.
* Propagation delays
 tPHL = output high to low
 tPLH = output low to high
 tP = (1/2)(tPHL+ tPLH) )
defines the speed of the
inverter.
t
Ch 10 MOS Digital
21
Propagation Delays and Switching Times
for NMOS Inverters
Load
Resistor
iR
+
+
vi=VOL
_
RD  2K
iC
vo
iD= 0
_
C
* Output goes from Low to High
 Drive transistor turns off
 Load resistor provides current to
charge up C.
V v 
dv
iC C o iR  DD o
dt
RD
Driver
VTh1 1.0 V
vot
W1 5m, L1 1m
K1 3.1x104
A
V2
OL
vo(t) VDDVDDVOLet/RDC

vo
tPLH = time to charge to the midpoint
½(VOH+VOL) = 1/2(5V + 0.95V) = 3.0V
etPLH/RDC3.0V
vo(tPLH
)V
V
V
DD
DD
OL
For
C10pF
,
VDD
3V
VOL=
0.95V
t
dv
1
o

 VDDvo RDCdt
V
0
tPLH
t
ECES 352 Winter 2007
V

V
DD
OL
tPLH
R
C
ln
D
V 3.0

 DD V
V0.95
V
5
2K
(10
pF
) ln
14nsec

V3.0
V
5

Ch 10 MOS Digital
22
Propagation Delays and Switching Times
for NMOS Inverters
Load
Resistor
iR
+
+
vi =VOH
_
RD  2K
iC
C
vo
iD
C
VTh1 1.0 V
K1 3.1x104


A
V2
D
RD
2
t
dv
1
o

dt


V

v

i
R
R
C
D D
D 0
VOH DD o
vo(t)VDDiDRDVDDiDRDVOHet/RDC
tPHL = time to discharge from
VOH
= VDD to
 (VOH+VOL) = 1/2(5V + 0.95V) = 3.0V
V

V
et /RC3
v
(
tPHL
)

iD
R

iD
R

V
.0
V
o
DD
D
DD
D
OH

PHL
D
For
C

10
pF
,
3V
VOL=
0.95V
D
vot


4A
2

3
.
1
x
10
(
5
V

1
V
)

5
mA
2
V
VDD
R
2
2
2
i

K
v
V

K
V

V
D
i
Th
OH
Th
vo
dt
iD Kvi VTh KVOHVTh a constant
!
W1 5m, L1 1m
_

Driver
* Output goes from High to Low
 Drive transistor turns on v = V
i
OH
 But load resistor continues to
provide some current so
V v 
dv
i C o i i  DD o i
tPHL
t
ECES 352 Winter 2007
V


idR

V
DD
D
OH
tPHL

R
C
ln
D


V

idR

3
.0
V
DD
D


5
V

5
mA
(2
K
)
5
V

2
K
(
10
pF
)ln
4
.5n
sec


5
V

5
mA
(
2
K
)

3
.
0
V


Ch 10 MOS Digital
23
Propagation Delays Time for NMOS Inverters
Load
Resistor
iR
+
vi=VOL
_
vo
iD= 0
_
C
*
Output goes from High to Low
 Drive transistor turns on to discharge
the capacitor but
 Load resistor continues to provide
current.


V

i
R

V
DD
d
D
OH
t

R
C
ln

4
.
5
n
se
PHL
D


V

i
R

3
.
0
V
DD
d
D


*
Average Propagation Time tPD
Driver
VTh1 1.0 V
W1 5m, L1 1m
K1 3.1x104
vo
A
V2
vo
VDD
3V
VOL=
0.95V
Output goes from Low to High
 Drive transistor turns off
 Load resistor provides current to
charge up C.


V

V
DD
OL
t

R
C
ln

14
n
sec
PLH
D


V

3
.
0
V
DD

RD  2K
iC
+
*

VDD
3V
tPLH
ECES 352 Winter 2007
t
VOL=
0.95V

1
1


t

t

t

4
.
5
n
sec

14
n
sec

10
n
se
PD
PHL
PLH
2
2
tPHL
Ch 10 MOS Digital
t
24
Propagation Delay for NMOS Inverter
*
Load
iC
iR
Driver
C
iD
Driver
iDS
R
S
vi = vGS = VOH =5 V
T
vo=VOL
=0.95V
P
ECES 352 Winter 2007
vDS
*
Output goes from High (VOH = 5V) to
Low (VOL = 0.95V)
 Driver transistor Q
(starts from P  R  S  T)
 At outset, Q is off (P), and
vDS1 = vo = VOH = 5V, vi < VTh
 Driver turns on (P to R) when vGS
is switched to VOH = 5 V.
 Driver initially is in saturation
mode, then eventually moves into
triode as capacitor discharges and
vo (= vDS) decreases
 Q moves along constant vGS
characteristic (R  S  T).
 Ends at (T) in triode region,
where vDS = vo = VOL = 0.95V.
 Load resistor continuously
providing current opposing
discharge of capacitor.
Output goes from Low to High
 Drive transistor is off
(vi = 0.95 V < VTh = 1.0 V
 Transistor moves from T  P as
the output voltage vo rises to 5 V.
vo =VOH = 5 V
Ch 10 MOS Digital
25
Power-Delay Product for NMOS Inverter
(E-MOSFET + Resistor Load)
* Average Propagation Time tPD


1
1


t

t

t

4
.
5
n
sec

14
n
sec

10
n
s
PD
PHL
PLH
2
2
* Average Power Dissipation P
C
(
0

10
mW
)
1


P

P

P


5
mW
HL
2
2
* Power-Delay Product DP
DP

P
t

5
mW
(
10
n
sec

50
p
PD
* Resistor’s Undesirable Effects
 Wasted power for transistor on (output low)
V

V
5
V

0
.
95
V
DD
OL
i



2
.
0
mA
and
P

10
mW
R
L
R
2
K
D
 Resistor provides limited charging current
 Maximum iR = 2 mA, but iR decreases
as vo rises.
 iR slows down discharge of C when
output goes low.
ECES 352 Winter 2007
* Problems with this inverter:
* Unequal noise margins!
NML = 0.05 V, NMH = 3.17 V
* Unequal transition times!
τPHL = 4.5 nsec, τPLH = 14 nsec
* Significant power dissipation!
Can we improve on this inverter ?
Ch 10 MOS Digital
26