Transcript Slide 1
Nanoimprint Lithography for Hybrid Plastic Electronics Michael C. McAlpine, Robin S. Friedman, and Charles M. Lieber Harvard UniVersity Chieh Chang EE 235 – Presentation I March 20, 2007 Introduction Efficient fabrication of integrated circuits Photolithography Reliable High-throughput processing Feature resolution: 100nm Complex and costly fabrication equipment Alternatives of nanoscale patterning Electron beam Scanning probe Extreme ultraviolet Dip pen Nanoimprint Scalable, parallel, cost-effective Feature resolution: sub-25nm Nanoimprint Thermoplastic NIL Heating process limits the application to flexible plastic substract. NIL @ room temperature on plastic substrate with nanometer scale resolution Combined with inorganic semiconductor nanowires to generate nanoscale transistor Schematic Plastic substrates coated with SiO2 and Lift-off resistor (LOR) were imprinted using a Si/SiO2 stamp. The NIL pattern was transferred to the substrate in successive RIE Metal deposition, and liftoff steps Key Issues The deposition of a resistor for room temperature imprinting Reproducibly imprinted at room temperature Cleanly removed from the inorganic stamp without antiadhesion agents Etched at controlled rates by RIE The SiO2 Improve metal adhesion Not affect flexibility Results (A) Optical image of S-D array and interconnect wires; scale bar, 100 um (B) Optical image of 200 nm SD lines and 1 um interconnect lines; scale bar, 25 um (C) SEM image of S-D array of 2um pitch, and 500nm gap; scale bar ,20 um (Inset) SEM image of 200 nm width channel lines; scale bar, 200nm Results (D) Optical image of patterned Mylar substrate (E) Optical image of hierarchically patterned arrays of gate electrodes; scale bar, 100 um (Inset) SEM image of a gate array block, where corner squares are alignment marks; scale bar, 5 um Bottom-up + Top-down A solution of p-type SiNWs were flowaligned in a direction perpendicular to the gate electrode arrays FET: 20 nm p-SiNW crossing an imprintpatterned metal gate Measurement Current versus S-D voltage (I-Vsd) data recorded on a typical crossed-junction pSiNW FET. The S-D contacts are ohmic. As Vg is increased, the slopes of the individual I-Vsd curves decrease as expected for a p-type FET. Measurement Plots of the conductance versus Vg. Vsd is 1V The transconductance of this device is 750 nS This value is within a factor of 2 of that recently reported for core/shell nanowire devices that were fabricated on conventional singlecrystal Si/SiO2 substrates. The device performance could be improved by decreasing the dopant concentration and/or minimizing trap states in the dielectric Summary This paper has demonstrated NIL of nanometer through millimeter-scale features on flexible plastic substrates over large areas at room temperature. The ambient temperature NIL patterning technique has been shown to produce uniform features in a parallel and repeatable manner Moreover, NIL has been combined with bottom up assembly to fabricate SiNW FETs on flexible plastic substrates with device performances similar to nanowire FETs fabricated on conventional single-crystal substrates. The development of simple and reproducible high-resolution patterning of plastics using NIL combined with the versatile function of nanowire building blocks could open up exciting opportunities over many length scales for plastic electronics and photonics.