Transcript Lecture 7 Overview - University of Delaware

Announcements
• Assignment 6 due on Friday
• Project ideas due today
– Need to try to place orders this week.
– Your responsibility when ordering parts includes: getting
them in time, getting correct part numbers, finding
replacements for obsolete parts, and checking
availability (no back orders, no large minimum
quantities).
– For chips, you want DIP (dual inline package), not SOIC
– If using digikey for many parts, make up an
order list, and send me the Web ID & Access
ID
Announcements
•
•
•
•
•
Joe: Game show Buzzer
Trisha & Matt: EMG (?)
Jamy: LED cube
Jingliang: Piezoelectric charger
Eric: Water printer(?)
Lecture 18 Overview
• Multivibrators
– Bistable: R-S latch
– Monostable: one-shots
– Astable: 555 Timer (today's lab)
The R-S latch
• Cross-coupled gates form an R-S latch with two stable
states (bistable multivibrator)
INPUT
OUTPUT
S
Q’
R
Q
A
B
A NOR B
0
0
1
1
0
0
0
1
0
1
1
0
S=1, R=0 : Q=1, Q'=0
S=0, R=1 : Q=0, Q'=1
S=0, R=0 : hold state
S=1, R=1 : unstable
http://fac-web.spsu.edu/cs/faculty/bbrown/web_lectures/sequential/
One-shot
• A monostable multivibrator can be very useful
• produces an output pulse with the correct voltage levels and of adjustable width
• 74121 one-shot (monostable multivibrator) non-retriggerable.
Output pulse width is determined by an external RC network
One-shot
• The 74121 is non-retriggerable - it ignores input transitions when the output
pulse is HIGH
• It is often more useful to use a retriggerable one-shot; e.g. 74LS122
For this
type of
input both
behave the
same
For this type:
Oscillators
Digital circuits also need clocks.
We can create a simple "relaxation oscillator" using the Schmitt trigger:
This sets the clock
period ( RC)
This sets the
threshold levels
This is an astable multivibrator (no stable state)
v+=vo/2
v-=vC
Oscillators
• For lowish frequencies (<1MHz), a cheap and reliable clock can be made with
a 555 timer chip.
555 Timer
555 Timer
transistor acts as a voltage
controlled switch that passes
current from "discharge" input
to ground when base voltage
is HIGH
Voltage divider
555 Timer
Vcontrol = 2/3 Vcc
Vtrig = 1/3 Vcc
Voltage divider
555 Timer
Alternatively, we can
set Vcontrol externally:
Control
Voltage
Vcontrol = Vcontrol
Vtrig = 1/2 Vcontrol
555 Timer
Two Comparators:
Output a HIGH voltage
level when the "+" input is
greater than the "-" input.
Vcontrol
Vtrig
Upper comparator:
Threshold input is
compared to Vcontrol
Lower comparator: Trigger
input is compared to Vtrig.
Results are passed to a
flipflop
555 Timer
Flipflop:
Stores the information of
which comparator last
passed it a high voltage.
S
Vcontrol
R
Vtrig
Q
If Threshold>Vcontrol ;
S=1
Output state is HIGH.
Transistor is switched on
If Trigger< Vtrig;
R=1
Output state is LOW
Transistor is switched off.
555 Timer:
Monostable
configuration.
Single pulse
B
• Initial state: flipflop is "set". Point C is HIGH.
• Transistor is on - passing capacitor charge to ground.
• When trigger input at A goes LOW, bottom comparator
triggers and E goes HIGH.
• Flipflop changes state: C goes LOW
• Transistor is off - capacitor starts charging (B) through R
• When point B reaches 2/3 Vcc, flipflop changes state,
transistor is on, capacitor discharges rapidly.
• Output pulse is just the inverse of C
• Width of output pulse = 1.1RC
D
C
trigger input
A
E
A
B
C
D
E
Capacitor voltage
FF output
upper comp.
lower comp.
555 Timer: Astable configuration
• In this mode, connect both comparator inputs to the
capacitor in order to generate a clock.
•Charge up through RA+RB, discharge through RB
• Capacitor charging and discharging times can be
controlled by resistor selection, in order to define the clock
period and duty cycle
555 Timer: Practical limits
• For reliable performance:
• The resistors RA and RB must be between 1kΩ and 3MΩ
• The capacitor C must be greater than 500pF
• Shortest period ~ 510-7, (Max frequency fmax= 2MHz)
• If RB>>RA, duty cycle ~50% (square wave oscillator)
• Power supply drift is not a problem - time constant is independent of
power supply - only depends upon resistor and capacitor values.
• Buffer at last stage can provide enough current to drive many TTL
loads