Transcript Elektroniczne Układy i Systemy Zasilania

SWITCH-MODE POWER
SUPPLIES AND SYSTEMS
Lecture No 7
Silesian University of Technology
Faculty of Automatic Control, Electronics
and Computer Sciences
Ryszard Siurek Ph.D., El. Eng.
Flyback converter
Ip
UIN
Zp
t

I0
IC
C
ZS
R0
U0
IT
CIN

D1
ID
T
T
Zp
n
ZS
transfer ratio
exceptional topology comprising transformer and output choke in one magnetic
component
topology with lowest compenet count – cheapest solution
L
IT
T
UIN
Zp
ID
ZS
D1
I0
IC
C
R0
U0
CIN
t
T
Compare to flyback switching regulator
Flyback converter basic relations analysis
Cycle I
UIN
- transistor T is ON
D1
Zp
ZS
UIN
n
I0
IC
C
iT (t) 
IT
UIN
t
Lp
Ipmax
U0
R0
t
IT
B
BS
T
Magnetic energy stored in the core
By the end of cycle I
Cycle II
-
transistor T is OFF
ID D 1
dUp
UIN
nU0
2
LpIpm
ax
E1 
2
Zp
ZS
U0
H
ID
I0
IC
C
U0
iD (t)  IDm ax 
IDmax
R0
t
U0
t
LS
T
t’
B
BS
IT=0
T
Magnetic energy recovered
from the core by the end of cycle II
2
LSIDm
ax
E2 
2
H
From energy balance :
2
2
LpIpm
ax LSIDm ax
E1  E2 

2
2
IDmax
(1)
U
iD (t)  IDm ax  0 t
LS
LS
(2)
I0
iD(t)
~
UC
Ro
U0
From equation (1) :
IDm ax  Ipm ax
Lp
LS
hence:
IDm ax  Ipm ax
L  Al  z2
but
Al -
core constant
Zp
I
n
Z S pm ax
U0 may be calculated also from energy balance:
2
2
LpR 0
LpIpm
ax U0

T  U0  Ipm ax
2
R0
2T
At the point of t’ U
0  IDm ax  0 t'
LS
t' 
IDm axL S
U0

ID(t’) = 0,
Ipm axn 
U0
Lp
n2 
(3)
hence:
Ipm axLp
nU0
(4)
valid only in case of discontinuous
flux (current) flow, it means t’ < T - t
U0   t' 
From equation (4) :
ID
IDmax
U0(R0)
U0
U’0(R’0 < R0)
LpR 0
t’
T
t
U0  Ipm ax
for R0 < R0cr (I0 > I0cr) the flux in the core does
2T
not decay to 0 – so called „continuous flux
U0

flow” starts


U 
 IN 
 n 




2
g2
2LfI0
Compare to flyback
regulator
U0 
UIN g
n 1 g
IT
g > 0,5
ITmax
g = 0,5
t
ID
g < 0,5
T
IDmax = nITmax
IDmax
IDmin = nITmin
I0kr
I0
IDmin
from the condition: IT  n  ID

U0 
UIN g
n 1 g
Real diagrams of flyback converters
recovery of energy stored in the leakage inductance
Dd
Zp=Za
Zp
CIN
ZS
D
C
R0
U0
Za
UIN
Cs
T
Ds
Rs
snubbar circuit for dumping
overvoltage spikes and reducing
transistor power losses
Advantages:
Energy stored in leakage inductace is recovered, transitor voltage does not exceed 2UIN
Disadvatages:
Complicated and expensive transformer
LL
D
LL
Rs
Cs
Leakage inductance measurement method
LL
Up
Zp
ZS
C
R0
U0
UIN
CIN
T
UT=Up+UIN
2
Up2
LLIpm
ax

T 
2
R
Up  Ipm ax
s
LLR s
2T
Disadvatages:
Energy stored in the leakage inductance is dissipated in resistor Rs, lower efficiency,
necessity of power resistor utilisation, component heating, possibility of transitor
voltage higher than 2UIN
Advantages:
Cheaper transformer, lack of extra overvoltage spikes due to residual leakage
inductance
This topology often used in low power converters up to 100W
Multi - output coverters
Flyback topology
ID1
D1
I01
ZS1 US1
ID2
Zp
UIN
R01 U01
C1
D2
I02
T
CIN
ZS2 US2
C2
R02 U02
Feedback
loop
In II cycle
U01 = US1
U02 = US2

U01
U02

US1
US2

z S1
z S2
In this topology output voltages are dependent only on the secondary numbers of
turns. In case of perfect magnetic coupling only one output voltage may be regulated to
obtain the regulation of other outputs.
Valid for discontinuous as well as continuous current flow
One of the cheapest and simple solution delivering several regulated output voltages.
Forward converter
D1
Da
L1
D2
ZS1
C
R01 U01
C
R02 U02
Zp
CIN
D3
Za
L2
UIN
D4
ZS2
T
n1 
U01 
U02 
UIN
n1
UIN
n2
g

g
zp
z S1
and n2 
zp
z S2
U01 n
z
 2  S1  n12
U02 n1 z S2
This relation only valid in case of cotinuous
magnetic flux (current) flow in L1 & L2
Coupled output inductors
D1
Dd
ZS1
L1
D2
C1
R01 U01
C2
R02 U02
Zp
CIN
D3
Za
L2
UIN
ZS2
D4
T
Equivalent output circuit valid for cycle I :
L1
UIN
n1
UIN
n2
U01  g
'
UL1
'
UL2
L2
U02  g
UIN
n1
UIN
n2
'  UIN  U  UIN  g UIN  UIN 1 g 
UL1
01
n1
n1
n1 n1
'  UIN  U  UIN  g UIN  UIN 1 g 
UL2
02
n2
n2
n2 n2

U'
z
L1  n2  S1
n1 z S2
U'
L2
Equivalent output circuit valid for cycle II:
L1
U01  U"L1
U"L1
U"L2
L2
g

"
U02  UL2
UIN
U'
U
z
L1  01  n1  n2  S1
U02 g UIN n1 z S2
U'
L2
n2
To achieve proper relation between output voltages the following condition
must be satisfied :
U'
U"
z
z S1 z
L1  L1  S1

 L1
z S2
z S2 zL2
U'
U"
L2
L2
In real circuit:
diode voltage drop and nonlinear diode characteristics have significant influence on
output voltages
-
-
influece of winding resistances
-
significant influence of leakage (poor winding coupling)
Detailed relations of turns number for particular windings are usually set by the way of
experiment in practice – equations presented above give only the rough approximation.
The other way of obtaining auxilliary regulated output voltages with low load
requirements :
D2
Da
D2
Zp=Za
C2
L2
R2 U2
L
Zp
CIN
D1
Zw
C
R0 U0
Zd
UIN
T
C2
L2
UIN
n
R2 U2
z2
L2
L
U0
zL
L
C2
U0
R2 U2
U2 
z2
zL
U0