Transcript UnnoPixelJapan150927x

Development of n+-in-p planar pixel
sensors for very high radiation
environments, designed to retain high
efficiency after irradiation
Y. Unno (KEK)
for
ATLAS-Japan Silicon Collaboration
and Hamamatsu Photonics K.K.
10th Hiroshima Symposium, 2015/9/27, Y. Unno
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Hybrid Planar Pixel Sensor Module
Pixel Sensor
HV
Undepleted
HV
Lightning?
Depleted
(p-bulk)
n+ implant
p+ implant
SnAg Bumps
GND
Frontend ASIC
GND Support structure
– Frontend ASIC and Pixel sensor can be optimized independently,
without compromise...
• 3 issues
– Radiation tolerant pixel sensor
• pursuing planar-process n+-in-p pixel sensor
– Bump-bonding
• Thin sensor (150 µm) – thin ASIC (150 µm)
– High voltage protection at the sensor edges
• against HV of ~1000 V
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Content
• Radiation-tolerant Planar Pixel Sensor
– Identification of inefficient regions in irradiated
sensors
– Optimization of pixel structure(s)
– Understanding underlying physics of the
inefficiency
• with technology CAD (TCAD) simulations
• Bump-bonding
– Latest development
• Not covered ...
– Edge protection
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KEK/HPK n-in-p Pixel Sensors
FE-I3 1-chip pixels
FE-I4 2-chip pixels
FE-I4 1-chip pixels
FE-I3 4-chip pixels
n-in-p 6” #2 wafer layout
(“Old” pixel structures)
n-in-p 6” #4 New wafer layout
(“New” pixel structures)
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“Old” Pixel Structures
K. Motohashi et al. HSTD9
(DOI: 10.1016/j.nima.2014.05.092)
Irradiation: n 1×1016 neq/cm2
at Ljubljana
Bias rail
Before irrad.
No bias rail
n 1×1016 neq/cm2
After irrad.
PolySi
routing
-1200 V
Irrad. sensors
• Severe efficiency loss at the boundary of pixels, under the bias rail
• Subtle efficiency loss at the routing of bias resistor
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Old Pixel Structures (Wafer #2)
Pixel implant/electrode
p-stop
Bias resistor
(#2 Wafer Layout)
Bias rail
Pixel size (FE-I4): 50 × 250 µm2
• Polysilicon resistor biasing structure
• Bias rail → along the boundary of pixels
• Bias resistor (PolySilicon) → encircled outside the pixel implant
– Why? Traditional thinking, technically safer design in silicon process
• Bias resistor and Bias rail are connected to the pixel electrode in DC,
– thus, both are at “ground potential” (and other effects?)
• Why do we lose efficiency at the bias rail and, in less extent, at the bias
resistor..., especially after irradiation?
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Optimization of Pixel Structures
(#4 Wafer Layout)
(#2 Wafer Layout)
Pixel size (FE-I4): 50 × 250 µm2 (Large offset)
(Wide p-stop)
• Bias rail → Removing from the boundary to “over” the pixel
electrode (large offset) or widening the p-stop (Wide p-stop).
– No bias rail along the boundary or reducing the “effect”.
• PolySilicon bias resistor → routing over the pixel elecrode.
– Removing another “ground potential” outside the pixel.
• Thus, “hiding” the traces with the pixel electrode or with the
p-stop.
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Results
with
Testbeams
Old design
(n 1×1016 neq/cm2)
1200V
CERN testbeam
D. Yamaguchi
• Beamtests
– CERN: 120 GeV p’s
• Pointing resol’n: s~8 µm
– DESY: 4 GeV e’s,
• Pointing resol’n: s~30 µm
• Comparison of “Area”
New design Irrad. KEK46 (Type10)
400V
– Width of the dip is due
to the pointing
resolution
– “Area” eliminates the
effect of resolution.
• Left-Right asymmetry is
very much improved.
100V
(p 5×1015 neq/cm2)
– Bias rail effect is nearly
eliminated.
DESY testbeam
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• “Old” design loses 2-3% eff. under the bias rail; 97-98% overall eff. .
NoC
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図 4.33
センサーの厚みと
放射線照射量を考慮に入れたバイアスレールのある境界部分の
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Understanding the Physics behind
• Usage of Semiconductor Technology CAD (TCAD)
program
– What is TCAD?
– Basically, it is an finite element analysis program with (a
jungle of) semiconductor physics.
– It can generate and evaluate the electric fields, in detail,
including e.g. inversion layer at the Oxide-Silicon interface
at the surface.
• Before/After irradiation can be approximated with 3
parameters effectively:
Doping concentration, Neff (cm-3)
Interface charge, Qf (cm-2)
Leakage current
Non irrad.
Irrad. (3x1015)
2.6⨉1012
2.5⨉1013
1⨉1010
1⨉1012
O(1)
O(1000)
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TCAD Geometry
Biasx0rail
x13
x7
x9 wEx1
wEx2
x11
wEx1
x14
Pixel electrode
x8
x10
wEx
wEx2
x12
wEx1
y3
y2
tAlu
y1 y0
tSio1
tNsub
y5
y4
x1
x3
x5
wNsub
wGap
wPsub
wGap
wNsub
tSio2
x6
x4
x2
tSi
y8
y6
tPback
y7
Si thickness
(µm)
Fluence
(neq/cm2)
Neff (ptype)(cm-3)
Nonirrad
Irrad
150
150
Null
3⨉1015
2.6⨉1012 2.5⨉1013
Vdep (Vapp) (V)
44 (100)
430 (430)
Interface
charge Qf (cm2)
1⨉1010
1⨉1012
Vdep = depletion voltage
Vapp = applied bias voltage
(Not to scale)
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TCAD Example: Electron Layer
• Creation of the inversion layer of “electrons” attracted
to the interface charge is simulated in TCAD.
Electron layer disappears near
the p-stop due to electric field.
Pixel implant
P-stop
(p-stop edge at -2 µm)
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Effect of Potential of Bias Rail
Non-irrad.
Irrad.
With bias rail (black)
No bias rail (Green)
– Electric field (Potential) between pixels
– near the surface (1 µm below the surface of Si in TCAD)
• Existence (Black) or non-existence (Green) of bias rail
(“ground potential”)
– has not affected the electric field in the silicon very much.
– “Ground potential” is not the source of the efficiency loss.
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Induced Charge – Ramo’s theorem
This is illustrated in the following schematic plot of the weighting field
in a strip detector (from Radeka)
•
A mobile charge in the presence of any number of
grounded electrodes, the induced charge QA at an
electrode A is
QA = q ×VqA
– where q is the charge in a position, VqA the
“weighting potential” of the electrode A at the
position of q.
•
In a finite time and with a readout circuitry,
instantaneous induced current, iA, is gradient of VqA
along the moving direction times drift velocity.
æ ¶VqA dx ö
¶VqA
iA = q
= qç
÷ = q × vx ×
dt
¶x
è ¶x dt ø
(From V. Radeka)
¶Vx
A speciality of our application:
vx = m Ex = m
Fast shaping of ~20 ns peaking time
¶x
dVqA
•
S e mi c o n d u c t o r
S L UO L e c t u r e s
De t e c t o r s
o n De t e c t o r
He l mu t h e Sr
2 3 , 1 9 9L8B N L
Although the final answer shall be obtained after → sensitive to the fast component
integrating the current, we can have physics insight,
qualitatively, from
Te c hni que s ,
Oc t o b e r
Ex , nx, VqA
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output_dis.dists0.E
Ex
Effect of the Bias Rail
output_dis.dists0.E
[ (V/cm) ]
VqA (Pixel)
6.70e+05
Ex
[V]
VqA (Pixel)
1.10e+06
1.82e+05
2.71e+05
4.96e+04
6.68e+04
1.35e+04
1.65e+04
3.67e+03
4.06e+03
1.00e+03
1.00e+03
output_dis.dists0.E
nx
[ (V/cm) ]
VqA (Bias rail)
6.70e+05
output_IrradWBS_dis.dists0.E
nx
[ (V/cm) ]
VqA (Bias rail)
1.10e+06
1.82e+05
2.71e+05
4.96e+04
6.68e+04
1.35e+04
1.65e+04
3.67e+03
4.06e+03
1.00e+03
1.00e+03
Non-irrad. Vapp=-100 V
•
•
Irrad. Va;pp=-430 V
In Irrad. situation, the“Weighting potential (of the bias rail)” is extending more in depth
where the drift path from deep region overlaps.
In Non-irrad., they are not overlapping due to the very low electric field region underneath
the bias rail.
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VqA (Bias rail)
Other Cases
VqA (Bias rail)
Wide p-stop, Irrad
Non-irrad. (Qf=1⨉1010)
Non-irrad. (Qf=1⨉1012)
• Wide p-stop:
– Effective to reduce “Weighting
potential”
• High interface charge:
– are not extending the “Weighting
potential”; Contrary, reducing it.
– A case of g irradiation
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Results from the g-irrad. modules
New latest results in POSTER
ID 21, K.Kimura et al.
p: ~3×1015 neq/cm2
g: ~2.4 MGy
Type2: Large offset (=Type10)
150 µm thick, p-irrad. (blue)
Preliminary
Type8: “Old” structure
320 µm thick, g-irrad. (red)
Type8, g irrad.
Preliminary
• Very little efficiency loss in the “Old” pixel structure
– after g irradiation.
• The cause of the efficiency loss is NOT due to the surface
damage, BUT due to the bulk damage effect.
– which confirms the prediction of the TCAD analysis.
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Efficiency Loss – Physics behind
• TCAD simulations show (at least qualitatively)
– The efficiency loss under the bias rail, of the irrad. device,
is caused by the bias rail acting as an (charge collecting)
electrode (through “weighting potential”+ Fast shaping)
– In “non-irrad.” device, the bias rail as an electrode is
“shielded” by the low electric field region (under the bias
rail) which has reduced “weighting potential” but also
deflecting the drifting carriers away from the “weighting
potential”.
– In “irrad.” device, strong electric field in the bulk has
reduced the low electric field region and also make the
drifting carriers to pass through large “weighting potential”
region.
– Increase of the Interface charge has not caused the
efficiency loss, which is confirmed with the testbeam
results of g-irrad. device.
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R&D of Bumpbonding (BB)
•
PIXEL2010
– Lead (PbSn) solder bumps
• Sensor/ASIC thickness: 320 µm/~700 µm
• Basically, no issue
•
HSTD8-2011: Y. Unno, et al.,
Nucl. Instr. Meth. A699 (2013) 72-77
HSTD8-2011
– Lead-free（SnAg) solder bumps
• Lead-free is the requirement in industry
– Observed large bump-resistance
– Solved with
• new under-bump-metalization (UBM)
• together with the removal of surface oxide
layer with Plasma etching (top-right Figure)
•
Daisy-chain samples
2012-2015
– Thick sensor/Thin ASIC: 320 µm/150 µm
• has been successful
– Thin sensor/Thin ASIC: 150 µm/150 µm
2x2 FE-I4
• for the reduction of materials, especially in
the inner layers of a tracker
– Observed disconnected bumps in large
area
• due to larger bowing in sensors and ASIC’s
than in thick ones
• Flattening sensor/ASIC helps but not
enough
• Optimization of the parameters in BB is not
enough
• Source is identified being in-sufficient
removal of the surface oxide of the SnAg
bumps
90Sr
source
illumination
Example of disconnected bumps in SnAg BB
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R&D of Bumpbonding (BB)
• HSTD10-2015
– An backup option with Indium bumps
2x2 FE-I4
• BB with Ni/In bumps has been
successful (example: right)
90Sr
source
illumination
– Further optimization of SnAg BB
process
• Removal of oxide layer just before the
BB
Example of Ni/In BB
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Summary
• Novel design of the pixel structure has improved the
efficiency loss due to the bias rail and bias resistor routing.
• Thus, we have succeeded the design of the n+-in-p planar
pixel sensors which retain high efficiency after irradiation.
• We have understood the underlying physics of the efficiency
loss under the bias rail:
– The bias rail is acting as an electrode, for the fast-shaping of signals.
– Large electric field in the bulk after radiation damage reduces the low
electric field region under the bias rail. The low electric field region
“shield”s the weighting potential and deflects the drifting carriers, e.g.,
in the non-irrad. device.
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Contributors
• ATLAS-Japan Silicon Group
– KEK, Tokyo Inst. Tech., Osaka Uni., Kyoto Uni. Edu.,
Uni. Tsukuba, Waseda Uni.
• Hamamatsu Photonics K.K.
• PPS collaboration
– AS CR, Prague, LAL Orsay, LPNHE / Paris VI, Uni.
Bonn, HU Berlin, DESY, TU Dortmund, Uni.
Goettingen, MPP and HLL Munich, Uni. UdineINFN, KEK, Tokyo Inst. Tech., IFAE-CNM, Uni.
Geneve, Uni. Liverpool, UC Berkeley, UNMAlbuquerque, UC Santa Cruz
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Backup Slides
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ATLAS Tracker Layouts
• Current inner tracker
– Pixels: 5-12 cm
• Si area: 2.7
m2
• IBL(2015): 3.3 cm
– Strips: 30-51 (B)/28-56 (EC) cm
• Si area: 62 m2
– Transition Radiation Tracker
(TRT): 56-107 cm
• Occupancy is acceptable for
<3x1034 cm-2s-1
• Phase-II at HL-LHC: 5x1034 cm-2s-
• Phase-II upgrade (LOI)
– Pixels: 4-25 cm
• Si area: 8.2 m2
– Strips: 40.-100 (B) cm
• Si area: 122 (B)+71(EC)=193 m2
• Major changes from LHC
– All silicon tracker
– Large increase of Si area
• both in Pixels and Strips
• ~ 3 × LHC ATLAS
1
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Particle fluences in HL-LHC
• ATLAS detector to design for
•
•
•
– Instantaneous lum.: 7x1034 cm-2s-1
– Integrated lum.: 6000 fb-1 (including safety factor 2 in dose rate)
– Pileup: 200 events/crossing
PIXELs (HL-LHC)
–
–
–
–
–
Inner: r=3.7 cm ~2.2x1016
Medium: r = 7.5 cm, ~6x1015
Med/Out: r=15.5 cm ~2x1015
Outer: r = 31 cm (?) ~1x1015
Charged:Neutrons ≥ 1
STRIPs (HL-LHC)
– Replacing Strip and TRT
– Short strip: r = 30 cm, e.g.
• ~1x1015
– Long strips: r = 60 cm,
• ~5×1014
– Neutrons:Charged ≥ 1
Short strips
Long strips
IBL (LHC)
– Insertable B-layer pixel
– r = 3.3 cm
• Flunece ~3x1015 neq/cm2
• at Int.L~300 fb-1
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Pixel Structures in #4 Wafer
• For your reference,
Type no. Pixel size (µm2) Bump pad Bias type PolySi routing No. Bias rail
1
1
2
2
Inside
3
1
4
2
5
6
Inside(*)
1
7
PolySi
Outside
8
9
1
50x250
End
10
2
11
1
Inside
12
2
13
1
14
15
Straight
16
PT
-17
Zigzag
18
19
None
-20
PT
Straight
End
21
1
PolySi
Inside(**)
22
2
23
PT
-Zigzag
25x500
24
2
Center
25
2
PolySi
Inside(**)
26
2
27
Staggered
1
28
End
None
--Inside(*) Al-PolySi overlap
Inside(**) PolySi running peripheral in one side
Offset
Large
Large
Small
Small
None
P-stop width Bias rail mat. Comment
Narrow
Al
Wide
Narrow
Large
Large
Small
Small
"Old" std
"New" std
Narrow
PolySi
Wide
None
Narrow
Wide
Large
Small
-None
Narrow
-Wide
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Al
PolySi
Large
Small
Large
Large
Large(*)
--
Al
Al
Narrow
PolySi
--
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Evaluation of New Pixel Structures
• Irradiation at CYRIC
– 70 MeV protons, Tohoku Univ., Japan
– 3 to 5 x 1015 neq/cm2
• Latest setup
– Irradiation box with 15 “push-pull” slots
– “Liquid” Nitrogen cooling evaporated-in-supply-line
Samples in the irradiation box at CYRIC
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