Transcript Hardware/Software Co-design Design of Hardware/Software Systems

Hardware/Software Co-design
Design of Hardware/Software
Systems
A Class Presentation for VLSI Course by :
Akbar Sharifi
Based on the work presented in :
PROCEEDINGS OF THE IEEE
1997
GIOVANNI DE MICHELI, FELLOW IEEE
RAJESH K.GUPTA, MEMBER, IEEE
-----------------------------------------------------------------Some Slides From :
RASSP Education & Facilitation Program
Module 14
Outline
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Typical Co-Design Process
Components of HS Problems
Partitioning
Scheduling
Co-Simulation
Typical Co-design Process
FSMdirected graphs
System
Description
(Functional)
Concurrent processes
Programming languages
Unified representation
(Data/control flow)
HW/SW
Partitioning
Another
HW/SW
partition
SW
Software
Synthesis
HW
Interface
Synthesis
System
Integration
Hardware
Synthesis
Instruction set level
HW/SW evaluation
Components of the Co-design
Problem
 Specification of the system
 Hardware/Software Partitioning
– Architectural assumptions - type of processor, interface style
between hardware and software, etc.
– Partitioning objectives - maximize speedup, latency requirements,
minimize size, cost, etc.
– Partitioning strategies - high level partitioning by hand, automated
partitioning using various techniques, etc.
 Scheduling
– operation scheduling in hardware
– Instruction scheduling in compilers
– Process scheduling in operating systems
 Modeling the hardware/software system during the design
process
Partitioning
 A first order of impact on the cost/performance of
the final design
 In embedded systems :
– Partition of system functionality into application-specific
hardware and software executing on processors
 In general purpose computing systems :
– Captured by instruction set
 In FPGAs :
– Performing technology mapping
Scheduling
 Hardware and software scheduling differ in
formulation and overall goals
 Assign an execution start time to each task in a set
 Tasks linked by some relations (e.g.
dependencies, priorities….)
 Important when several modules in the partition
share a single hw unit
 Tasks execution requires the use of resources that
can be limited in number
 Serialization of some task execution
Operation Scheduling in Hardware
 The techniques have been implemented in CAD
tools
 Operations are assumed to take a known, integer
number of cycles to execute
 Integer linear programming
 The usual goal : minimize the overall execution
latency
 Satisfying the precedence and resource constraints
 heuristic approaches:
– list scheduling,
– force directed scheduling
Scheduling
 Instruction scheduling in hardware
– define a linear order of instructions
– instruction selection and register allocation
– goal: minimize code size and spills to memory
 Coupling between scheduling
– Pipelined microprocessors
– Pipeline hazard avoidance
 Process scheduling in operating systems
– SJF
– Roundrobin
– FIFO
Co-simulation
 An HDL (VHDL or Verilog) simulation environment is used
to perform behavioral simulation of the system hardware
processes
 A Software environment (C or C++) is used to develop the
code
 SW and HW execute as separate processes linked through
UNIX IPC (interprocessor communications) mechanisms
(sockets)
Verilog Co-simulation Example
Verilog HW Simulator
Module: Application
specific hardware
HW
proc 1
HW
proc 2
SW
proc 1
Module: Bus Interface
UNIX
sockets
Verilog PLI
SW
proc 2
Software processes
communicate with
hardware simulator
via UNIX sockets
Verilog PLI (programming
language interface) serves as
translator, allowing hardware
simulation models to
communicate with software
processes.
VHDL Co-simulation Example
VHDL Simulator
Hardware Model in VHDL:
RS232
module
VME
module
VHDL Foreign Language
Interface
Software processes
communicate with
hardware simulator
via foreign language
interface
SW
proc 1
SW
proc 2
Allowing hardware
simulation models to
“cosimulate” with software
processes.
 Hardware/Software co-design is the key design
technology for digital systems
References
 Hardware/Software Co-Design, 1996. (Codes/CASHE
'96), Proceedings., Fourth International Workshop on
 Hardware/Software Codesign of Embedded Systems,
Design Modeling and Design Verification
UCSD computer science professor Rajesh Gupta and
Cal-(IT)² researcher Ingolf Krueger