Transcript ch13
Chapter 13: I/O Systems Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013 Chapter 13: I/O Systems Overview I/O Hardware Application I/O Interface Kernel I/O Subsystem Transforming I/O Requests to Hardware Operations STREAMS Performance Operating System Concepts – 9th Edition 13.2 Silberschatz, Galvin and Gagne ©2013 Objectives Explore the structure of an operating system’s I/O subsystem Discuss the principles of I/O hardware and its complexity Provide details of the performance aspects of I/O hardware and software Operating System Concepts – 9th Edition 13.3 Silberschatz, Galvin and Gagne ©2013 Overview I/O management is a major component of operating system design and operation Important aspect of computer operation I/O devices vary greatly Various methods to control them Performance management New types of devices frequent Ports, busses, device controllers connect to various devices Device drivers encapsulate device details Present uniform device-access interface to I/O subsystem Operating System Concepts – 9th Edition 13.4 Silberschatz, Galvin and Gagne ©2013 I/O Hardware Incredible variety of I/O devices Storage Transmission Human-interface Common concepts – signals from I/O devices interface with computer Port – connection point for device eg serial port Bus –set of wires and a rigidly defined protocol that specifies a set of messages. Daisy chain is a chain of devices connected to the computer system PCI bus common in PCs and servers, PCI Express (PCIe) expansion bus connects relatively slow devices Controller (host adapter) – electronics that operate port, bus, device Sometimes integrated Sometimes separate circuit board (host adapter) Contains processor, microcode, private memory, bus controller, etc – Some talk to per-device controller with bus controller, microcode, memory, etc Operating System Concepts – 9th Edition 13.5 Silberschatz, Galvin and Gagne ©2013 A Typical PC Bus Structure Operating System Concepts – 9th Edition 13.6 Silberschatz, Galvin and Gagne ©2013 Disk Controller Operating System Concepts – 9th Edition 13.7 Silberschatz, Galvin and Gagne ©2013 How does the processor give commands and data to a controller? Controller has one or more registers for data and control signals. The processor communicates with the controller by reading and writing bit patterns in these registers. This is done by special I/O instructions that specify transfer of byte to an I/O port address-programmed I/O Which in turn triggers bus lines to select the proper device and move bits into or out of device registers Alternatively memory mapped I/O can be used by device controllers Operating System Concepts – 9th Edition 13.8 Silberschatz, Galvin and Gagne ©2013 Device I/O Port Locations on PCs (partial) PCs used both programmed I/O and memory mapped I/O. Operating System Concepts – 9th Edition 13.10 Silberschatz, Galvin and Gagne ©2013 Registers used in I/O port Status: contains bits that can be read by the host. Eg:- whether a command completed Control: written by the host to start a command o to change the mode of a device: Eg:- changing the type of communication Data-in: read by host to get input Data-out: written by host to send output Operating System Concepts – 9th Edition 13.11 Silberschatz, Galvin and Gagne ©2013 Polling Polling is done by handshaking Example 2 bits are used to coordinate the producer consumer relationship between the controller and host. Buzy bit with controller and command ready bit by host For each byte of I/O 1. The host repeatedly reads the busy bit of the controller until it becomes clear. 2. When clear, the host writes in the command register and writes a byte into the data-out register. 3. The host sets the command-ready bit (set to 1). 4. When the controller senses command-ready bit is set, it sets busy bit. 5. The controller reads the command register and since write bit is set, it performs necessary I/O operations on the device. If the read bit is set to one instead of write bit, data from device is loaded into data-in register, which is further read by the host. 6. The controller clears the command-ready bit once everything is over, it clears error bit to show successful operation and reset busy bit (0). Step 1 is busy-wait cycle to wait for I/O from device Reasonable if device is fast But inefficient if device slow Operating System Concepts – 9th Edition 13.12 Silberschatz, Galvin and Gagne ©2013 Interrupts Polling can happen in 3 instruction cycles Read status, logical-and to extract status bit, branch if not zero How to be more efficient if non-zero infrequently? CPU Interrupt-request line triggered by I/O device Interrupt handler receives interrupts Checked by processor after each instruction Maskable to ignore or delay some interrupts Interrupt vector to dispatch interrupt to correct handler Context switch at start and end Based on priority Some nonmaskable Interrupt chaining if more than one device at same interrupt number Operating System Concepts – 9th Edition 13.13 Silberschatz, Galvin and Gagne ©2013 Interrupt-Driven I/O Cycle Operating System Concepts – 9th Edition 13.14 Silberschatz, Galvin and Gagne ©2013 Intel Pentium Processor Event-Vector Table Operating System Concepts – 9th Edition 13.15 Silberschatz, Galvin and Gagne ©2013 Interrupts (Cont.) Interrupt mechanism also used for exceptions Terminate process, crash system due to hardware error Page fault executes when memory access error System call executes via trap to trigger kernel to execute request Multi-CPU systems can process interrupts concurrently If operating system designed to handle it Used for time-sensitive processing, frequent, must be fast Operating System Concepts – 9th Edition 13.16 Silberschatz, Galvin and Gagne ©2013 Direct Memory Access Used to avoid programmed I/O (one byte at a time) for large data movement Requires DMA controller Bypasses CPU to transfer data directly between I/O device and memory OS writes DMA command block into memory Source and destination addresses Read or write mode Count of bytes Writes location of command block to DMA controller Bus mastering of DMA controller – grabs bus from CPU Cycle stealing from CPU but still much more efficient When done, interrupts to signal completion Version that is aware of virtual addresses can be even more efficient - DVMA Operating System Concepts – 9th Edition 13.17 Silberschatz, Galvin and Gagne ©2013 Six Step Process to Perform DMA Transfer Operating System Concepts – 9th Edition 13.18 Silberschatz, Galvin and Gagne ©2013 Application I/O Interface I/O system calls encapsulate device behaviors in generic classes Device-driver layer hides differences among I/O controllers from kernel New devices talking already-implemented protocols need no extra work Each OS has its own I/O subsystem structures and device driver frameworks Devices vary in many dimensions Character-stream or block Sequential or random-access Synchronous or asynchronous (or both) Sharable or dedicated Speed of operation read-write, read only, or write only Operating System Concepts – 9th Edition 13.19 Silberschatz, Galvin and Gagne ©2013