Transcript Lecture 1: Overview

Course Information
Operating System
Fall 2006
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Instructor Information
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Office: 1N-214
Tel:(718) 982-2841
Email:[email protected]
Webpage:
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http://www.cs.csi.cuny.edu/~yumei/
Course webpage:
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http://www.cs.csi.cuny.edu/~yumei/csc718
/csc718Fall06.html
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Schedule
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Course
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Regularly scheduled conference hour
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Monday, 8:20pm-10:00pm
Room: 2N104
1 hour
supplemental independent study
Office hour:
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Monday 7:00pm - 8:00pm
Wednesday 1:30pm - 3:30pm
or by special appointment
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Textbook
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Operating System Concepts by
Silberschatz, Galvin, and Gagne,
seventh edition, John Wiley & Sons,
ISBN 0-471-69466-5.
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Course Content
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Overview:
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Review of computer organization
Overview of operating system
Process management:
Multithreading
real-time scheduling
synchronization, and concurrency;
interaction of concurrent processes;
network management and security;
Protection;
distributed system issues Processes
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Homework
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There are four homework assignments.
Homeworks will focus on how to use/program
with operating system mechanisms.
Homework assignments will be assigned
during class and also posted on the course
Web-page:
http://www.cs.csi.cuny.edu/~yumei/csc
718/csc718Fall06.html
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Homework (cont.)
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The solution to each homework may include the
source code and a report showing the result.
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The source code must be turned in by email to
[email protected].
The report can be submitted either per email or be handed
in a hard-copy at the beginning of the class.
Handwritten or typed report will be accepted.
Solutions must be readable(especially handwriting!!!), clear,
concise and complete.
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Project
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One course project
Two goals:
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Tasks:
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help you learn more about doing research in
general.
give you the opportunity to study a particular area
of OS in greater detail.
selecting an problem, designing, implementing,
and evaluating a solution, and submitting your
report.
list of suggestions
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Grade
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The exams may test on material covered only in class
and on material covered only in the reading
assignments.
Your grade will be based approximately, as follows.
These percentages are tentative and subject to
change.
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20%
15%
15%
15%
35%
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Homeworks
Projects
Midterm Exam #1
Midterm Exam #2
Final
Class participation is essential to succeed in this
course.
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Policy
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DO NOT USE pencils to write down your solutions for the
homework, project or exams
Check the marks in a homework, project or an exam and report
errors promptly. Make sure you report such problems to the
instructor within four weeks from receipt but no later than
Dec.16, 2005 .
Homework assignments are due at the start of class on their
due date. No later solutions will be taken into consideration!
The work you turn in MUST BE your own personal work,
composed and written by you.
DO NOT OBTAIN YOUR SOLUTION THROUGH THE INTERNET.
Collaboration of any kind is NOT allowed in the in-class exams
(midterms, and final).
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Lecture 1: Review of
Computer Organization
Operating System
Fall 2006
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What is Operating System?
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Operating system is a program that acts
as an intermediary between a user of a
computer and the computer hardware.
Main GOALS of an OS:
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To make the computer system convenient
to use
To use the computer hardware in an
efficient manner
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Four Elements of a Computer
System
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Processor (CPU)
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Main Memory
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Stores data and programs
RAM - random access memory
I/O Modules
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Control the operation of the computer and its data processing
functions.
Auxiliary storage like disk drives, tape drives
Printers, terminals, monitors
System Bus
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Provides for transfer of data among processors, main memory, and
I/O modules
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Computer Organization
MAIN MEMORY
CPU
PC
MAR
IR
MBR
System
Bus
0
1
…
Instruction
Execution
Unit
I/O AR
I/O BR
I/O module
buffer
Instruction
Instruction
…
DATA
DATA
…
n-2
n-1
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CPU (Processors) Registers
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A processor includes a set of registers that
provide a level of memory faster than main
memory.
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User-visible Registers
Control and Status Registers
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User-visible Registers
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Many instructions operate on data sitting on working
registers.
Since registers are faster than main memory, it is
better that data be moved to registers before
operating on them.
May be referenced by the machine language that the
processor executes
available to all programs - application programs and
system programs.
Types of registers:
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Data registers
Address registers
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For
For
For
For
indirect addressing
index register
segment pointer
stack pointer
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Control and Status Registers
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Program Controller (PC) – contains the address of an instruction
to be fetched
Instruction Register (IR) – contains the instruction most recently
fetched
Memory Address Register (MAR)
Memory Buffer Register (MBR)
I/O Address Register (I/O AR)
I/O Buffer Register (I/O BR)
Processor Status Word (PSW)
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condition codes or flags
interrupt enable/disable
user/supervisor mode
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Instruction Cycle
Start
Fetch Cycle
Execute Cycle
Fetch next
instruction
Execute
instruction
Halt
Opcode
Address of Operand
Instruction Format
Sign
magnitude
Integer Format
Sign exponent
magnitude
Floating point Format
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Actions of CPU
(Types of Instructions)
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Processor-Memory Data Transfer
Processor-I/O Data Transfer
Data Processing
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Arithmetic or logic operation on data
Control
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Alter sequence of execution
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Interrupts
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An interruption of the normal sequence
of execution
Improve processing efficiency
Allows the processor to execute other
instructions while an I/O operation is in
progress
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Interrupts - Classes of Interrupts
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Program
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arithmetic overflow or underflow
division by zero
attempt to execute an illegal machine instruction
reference outside user’s memory space
Timer
I/O
Hardware Failure
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Interrupts –Interrupt Handler
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A program that determines nature of
the interrupt and performs whatever
actions are needed
Control is transferred to this program
Generally part of the operating system
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Interrupt Timeline
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Interrupts and the Instruction
Cycle
Start
Fetch Cycle
Execute Cycle
Fetch next
instruction
Execute
instruction
Interrupts
Enabled
Check for interrupt
and process interrupt
Interrupts
Disabled
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Interrupt Cycle
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Processor checks for interrupts
If no interrupts, fetch the next instruction for
the current program
If an interrupt is pending, suspend execution
of the current program, and execute the
interrupt handler
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Program Flow of Control
without and with Interrupts
User Program
I/O Program
(1)
WRITE
(2)
WRITE
(3)
(4)
I/O Command
(5)
END
WRITE
User Program
I/O Program
(4)
(1)
WRITE
(2)
I/O Command
Interrupt Handler
WRITE
(5)
(3)
END
WRITE
No interrupts
Interrupts
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Simple Interrupt Processing
Hardware
Device controller or other
Hardware generates an interrupt
Software
Save remainder of
process state information
Processor finished
execution of current instruction
Process interrupt
Processor signals
acknowledgement of interrupt
Processor pushes PSW
and PC onto control stack
Processor loads new
PC value based on interrupt
Restore process
state information
Restore old
PSW and PC
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Multiple Interrupts
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Two methods:
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Disable other interrupts while processing
one interrupt
Assign priorities to different interrupts.
Interrupts at higher priority can interrupt
lower ones
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Memory
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Registers
Cache
Main memory
Electronic disk
Magnetic disk
Optical disk
Magnetic tapes
volatile
Decreasing cost per bit
Increasing capacity
Increasing access time
nonvolatile
Decreasing frequency of access
of the memory by the processor
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Performance of Various Levels of
Storage
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Movement between levels of storage
hierarchy can be explicit or implicit
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Caching
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Important principle, performed at many levels in a
computer (in hardware, operating system, software)
Information in use copied from slower to faster
storage temporarily
Faster storage (cache) checked first to determine if
information is there
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If it is, information used directly from the cache (fast)
If not, data copied to cache and used there
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Cache
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Invisible to operating system
Increase the speed of memory
Processor speed is faster than memory
speed
Contain a portion of main memory
CPU
Word
Transfer
Cache
Block
Transfer
Main
memory
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Cache Design
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Cache size
Block size
Mapping function
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Replacement algorithm
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Determine which cache location the block will occupy
Determines which block to replace
Least-Recently-Used(LRU) algorithm
Write policy
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When the memory write operation takes place
Can occur every time block is updated
Can occur only when block is replaced
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I/O Communication Techniques
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Programmed I/O
Interrupt-Driven I/O
Direct Memory Access (DMA)
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I/O Communication Techniques
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Programmed I/O
Interrupt-Driven I/O
Direct Memory Access (DMA)
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Programmed I/O
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I/O module performs
the action, not the
processor
Sets appropriate bits in
the I/O status register
No interrupts occur
Processor checks status
until operation is
complete
Issue Read
command
to I/O module
CPU->I/O
Read status of
I/O module
I/O -> CPU
Not
ready
Check status
Error
condition
ready
Read word from
I/O -> CPU
I/O module
Write word into
CPU->memory
Main memory
no
Done?
yes
Next instruction
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I/O Communication Techniques
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Programmed I/O
Interrupt-Driven I/O
Direct Memory Access (DMA)
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Interrupt-Driven I/O
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Processor is interrupt
when I/O module
ready to exchange
data
Processor is free to do
other work
No needless waiting
Consumes a lot of
processor time
because every word
read or written passes
through the processor
Issue Read
CPU->I/O
command
Do something
to I/O module
else
Read status of
Interrupt
I/O module I/O -> CPU
Check status
Error
condition
ready
Read word from
I/O -> CPU
I/O module
Write word into
CPU->memory
Main memory
no
Done?
yes
Next instruction
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I/O Communication Techniques
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Programmed I/O
Interrupt-Driven I/O
Direct Memory Access (DMA)
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Direct Memory Access
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Transfer a block of data
directly to or from
memory
An interrupt is sent when
the task is complete
The processor is only
involved at the beginning
and end of the transfer
Issue Read
CPU->DMA
command
Do something
to I/O module
else
Read status of
Interrupt
DMA module DMA -> CPU
Next instruction
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End of lecture 1
Thank you!
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