Transcript CS533 Concepts of Operating Systems

CS533 Concepts of Operating Systems
Class 6
The Performance of MicroKernel Based Systems
Micro-kernels and Binary Compatibility
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Emulation libraries
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Trampoline mechanism
Single server architecture
Multi-server architecture
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IPC overhead proportional to number of servers
(independent protection domains)
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Micro-kernels must optimize IPC
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Liedtke argues Mach’s overhead is due to poor implementation!
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Optimized IPC implementation in L3
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Architectural level
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Algorithmic level
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Thread Identifier, Virtual Queues, Timeouts/Wakeups, Lazy
Scheduling, Direct Process Switch, Short Messages.
Interface level
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System Calls, Messages, Direct Transfer, Strict Process Orientation,
Control Blocks.
Unnecessary Copies, Parameter passing.
Coding level
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Cache Misses, TLB Misses, Segment Registers, General Registers,
Jumps and Checks, Process Switch.
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L3 IPC Performance vs Mach IPC
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But Is That Enough?
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What is the impact on overall system performance?
Haertig et al explore performance and extensibility
of L4-based Linux OS vs Mach-based Linux and
native Linux
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L4Linux – a micro-kernel based Linux
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Fully binary compliant with Linux/X86
No changes to the architecture-independent parts
of Linux
No Linux-specific modifications to the L4 kernel
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L4Linux – Design & Implementation
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Linux implemented as a single Linux server in a μ-kernel task
μ-kernel tasks used for Linux user processes
A single L4 thread in the Linux server handles system calls and
page faults. This thread is multiplexed (treated as a virtual CPU)
On booting, the Linux server requests memory from its pager,
which maps physical memory into the server’s address space
The Linux server then acts as the pager for the user processes
it creates
o
L4 converts user-process page faults into an RPC to the Linux server, which
maps pages from its address space to the user process
Interrupt Handling
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Linux top halves are implemented as one server thread per
interrupt source
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L4 converts a hardware interrupt to a message to the appropriate thread
Linux bottom halves all execute in a single high priority thread
Linux interrupt threads have a higher priority than the main
thread
o
avoids concurrent execution of Linux code on a uniprocessor
System Calls
System calls implemented as IPC between user process and the
Linux server
Modified libc.so or libc.a avoid trap instructions and use L4 IPC
instead to call the Linux server
User-level exception handler (trampoline) emulates the native
system call ‘trap’ instruction for binary compatibility
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L4 redirects trap to emulation library which then used L4 IPC to call the
Linux server
Signals
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Each user process has a separate signal-handler thread
Linux server’s delivers a signal by sending a message to the
user process’s signal-handler thread
The signal-handler causes the user process’s main thread to
save it’s state and enter Linux by manipulating the main
thread’s SP and PC
Scheduling
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All thread scheduling is done by the L4 kernel
The Linux server’s schedule() routine is only used for
multiplexing the Linux server’s Main thread across concurrent
Linux system calls
Experiment
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What is the penalty of using L4Linux?
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Does the performance of the underlying microkernel matter?
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Compare L4Linux to native Linux
Compare L4Linux to MkLinux
Does co-location improve performance?
o
Compare L4Linux to an in-kernel version of MkLinux
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Microbenchmarks
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measured system call overhead on shortest system
call “getpid()”
Linux
L4Linux
L4Linux(trampoline)
MkLinux (in kernel)
MkLinux (user)
223 cycles
526 cycles
753 cycles
2050 cycles
14710 cycles
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Microbenchmarks (cont.)
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Measures specific system calls to determine basic performance.
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Macrobenchmarks
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measured time to recompile Linux server
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Macrobenchmarks (cont.)
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Next use a commercial test suite to simulate a system under full
load.
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Performance Analysis
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L4Linux is, on average 8.3% slower than native Linux.
Only 6.8% slower at maximum load.
MkLinux: 49% slower on average, 60% at maximum.
Co-located MkLinux: 29% slower on average, 37% at
maximum
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Conclusion?
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Can hardware-based protection be made to work
efficiently enough?
Did these experiments explore the cost of “fine
grained” protection?
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Spare Slides
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The IPC Dilemma
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IPC is very import in μ-kernel design
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Increases modularity, flexibility, security and scalability.
Past implementations have been inefficient.
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Message transfer takes 50 - 500μs.
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The L3 (μ-kernel based) OS
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A task consists of:
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Threads
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Dataspaces
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Communicate via messages that consist of strings and/or
memory objects.
Memory objects.
Address space
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Where dataspaces are mapped.
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Redesign Principles
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IPC performance is the Master.
All design decisions require a performance discussion.
If something performs poorly, look for new techniques.
Synergetic effects have to be taken into considerations.
The design has to cover all levels from architecture down to coding.
The design has to be made on a concrete basis.
The design has to aim at a concrete performance goal.
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Achievable Performance
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A simple scenario
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Thread A sends a null message to thread B
Minimum of 172 cycles
Will aim at 350 cycles (7 μs)
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Will actually achieve 250 cycles (5 μs)
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Levels of the redesign
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Architectural
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Algorithmic
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Thread Identifier, Virtual Queues, Timeouts/Wakeups, Lazy Scheduling,
Direct Process Switch, Short Messages.
Interface
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System Calls, Messages, Direct Transfer, Strict Process Orientation,
Control Blocks.
Unnecessary Copies, Parameter passing.
Coding
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Cache Misses, TLB Misses, Segment Registers, General Registers, Jumps
and Checks, Process Switch.
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Architectural Level
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System Calls
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Expensive! So, require as few as possible.
Implement two calls:
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Call
Reply & Receive Next
Combines sending an outgoing message with waiting for an
incoming message.
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Schedulers can handle replies the same as requests.
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Messages
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Complex Messages:
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A Complex Message
Direct String, Indirect Strings (optional)
Memory Objects
Used to combine sends if no reply is needed.
Can transfer values directly from sender’s variable to receiver’s variables.
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Direct Transfer
User A
Kernel
User B
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Each address space has a fixed kernel accessible part.
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Messages transferred via the kernel part
User A space -> Kernel -> User B space
Requires 2 copies.
Larger Messages lead to higher costs
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Shared User Level memory (LRPC, SRC RPC)
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Security can be penetrated.
Cannot check message’s legality.
Long messages -> address space becoming a critical
resource.
Explicit opening of communication channels.
Not application friendly.
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Temporary Mapping
User A
Kernel
User B
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L3 uses a Communication Window
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Only kernel accessible, and exists per address space.
Target region is temporarily mapped there.
Then the message is copied to the communication window and ends up in
the correct place in the target address space.
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Temporary Mapping
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Must be fast!
2 level page table only requires one word to be copied.
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pdir A -> pdir B
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One thread
TLB must be clean of entries relating to the use of the
communication window by other operations.
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TLB is always “window clean”.
Multiple threads
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Interrupts – TLB is flushed
Thread switch – Invalidate Communication window entries.
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Strict Process Orientation
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Kernel mode handled in same way as User mode
One kernel stack per thread
May lead to a large number of stacks
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Minor problem if stacks are objects in virtual memory
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Thread Control Blocks (tcb’s)
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Hold kernel, hardware, and thread-specific data.
Stored in a virtual array in shared kernel space.
User area
Kernel area
tcb
Kernel stack
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Tcb Benefits
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Fast tcb access
Saves 3 TLB misses per IPC
Threads can be locked by unmapping the tcb
Helps make thread persistent
IPC independent from memory management
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Algorithmic Level
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Thread ID’s
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L3 uses a 64 bit unique identifier (uid) containing the thread
number.
Tcb address is easily obtained
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anding the lower 32 bits with a bit mask and adding the tcb base
address.
Virtual Queues
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Busy queue, present queue, polling-me queue.
Unmapping the tcb includes removal from queues
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Prevents page faults from parsing/adding/deleting from the queues.
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Algorithmic Level
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Timeouts and Wakeups
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Operation fails if message transfer has not started t ms after
invoking it.
Kept in n unordered wakeup lists.
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A new thread’s tcb is linked into the list τ mod n.
Thread with wakeups far away are kept in a long time wakeup list
and reinserted into the normal lists when time approaches.
Scheduler will only have to check k/n entries per clock interrupt.
Usually costs less the 4% of ipc time.
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Algorithmic Level
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Lazy Scheduling
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Only a thread state variable is changed (ready/waiting).
Deletion from queues happens when queues are parsed.
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Reduces delete operations.
Reduces insert operations when a thread needs to be inserted
that hasn’t been deleted yet.
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Algorithmic Level
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Short messages via registers
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Register transfers are fast
50-80% of messages ≥ 8 bytes
Up to 8 byte messages can be transferred by registers
with a decent performance gain.
May not pay off for other processors.
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Interface Level
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Unnecessary Copies
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Message objects grouped by types
Send/receive buffers structured in the same way
Use same variable for sending and receiving
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Avoid unnecessary copies
Parameter Passing
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Use registers whenever possible.
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Far more efficient
Give compilers better opportunities to optimize code.
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Code Level
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Cache Misses
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Cache line fill sequence should match the usual data access
sequence.
TLB Misses
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Try and pack in one page:
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Ipc related kernel code
Processor internal tables
Start/end of Larger tables
Most heavily used entries
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Coding Level
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Registers
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Segment register loading is expensive.
One flat segment coving the complete address space.
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Jumps and Check
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On entry, kernel checks if registers contain the flat descriptor.
Guarantees they contain it when returning to user level.
Basic code blocks should be arranged so that as few jumps are taken as
possible.
Process switch
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Save/restore of stack pointer and address space only invoked when really
necessary.
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L4 Slides
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Introduction
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μ-kernels have reputation for being too slow,
inflexible
Can 2nd generation μ-kernel (L4) overcome
limitations?
Experiment:
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Port Linux to run on L4 (Mach 3.0)
Compared to native Linux, MkLinux (Linux on 1st gen Mach
derived μ-kernel)
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Introduction (cont.)
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Test speed of standard OS personality on top of fast μ-kernel:
Linux implemented on L4
Test extensibility of system:
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pipe-based communication implemented directly on μ-kernel
mapping-related OS extensions implemented as user tasks
user-level real-time memory management implemented
Test if L4 abstractions independent of platform
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L4 Essentials
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Based on threads and address spaces
Recursive construction of address spaces by user-level servers
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Initial address space σ0 represents physical memory
Basic operations: granting, mapping, and unmapping.
Owner of address space can grant or map page to another
address space
All address spaces maintained by user-level servers (pagers)
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L4Linux – Design & Implementation
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Fully binary compliant with Linux/X86
Restricted modifications to architecture-dependent
part of Linux
No Linux-specific modifications to L4 kernel
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L4Linux – Design & Implementation
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Address Spaces
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Initial address space σ0 represents physical memory
Basic operations: granting, mapping, and unmapping.
L4 uses “flexpages”: logical memory ranging from one
physical page up to a complete address space.
An invoker can only map and unmap pages that have been
mapped into its own address space
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L4Linux – Design & Implementation
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L4Linux – Design & Implementation
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Address Spaces (cont.)
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I/O ports are parts of address spaces.
Hardware interrupts are handled by user-level processes.
The L4 kernel will send a message via IPC.
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L4Linux – Design & Implementation
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The Linux server
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L4Linux will use a single-server approach.
A single Linux server will run on top of L4, multiplexing a
single thread for system calls and page faults.
The Linux server maps physical memory into its address
space, and acts as the pager for any user processes it
creates.
The Server cannot directly access the hardware page
tables, and must maintain logical pages in its own address
space.
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L4Linux – Design & Implementation
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Interrupt Handling
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All interrupt handlers are mapped to messages.
The Linux server contains threads that do nothing but wait
for interrupt messages.
Interrupt threads have a higher priority than the main
thread.
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L4Linux – Design & Implementation
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User Processes
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Each different user process is implemented as a different
L4 task: Has its own address space and threads.
The Linux Server is the pager for these processes. Any
fault by the user-level processes is sent by RPC from the
L4 kernel to the Server.
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L4Linux – Design & Implementation
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System Calls
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Three system call interfaces:
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A modified version of libc.so that uses L4 primitives.
A modified version of libc.a
A user-level exception handler (trampoline) calls the
corresponding routine in the modified shared library.
The first two options are the fastest. The third is
maintained for compatibility.
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L4Linux – Design & Implementation
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Signalling
o
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Each user-level process has an additional thread for signal
handling.
Main server thread sends a message for the signal
handling thread, telling the user thread to save it’s state
and enter Linux
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L4Linux – Design & Implementation
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Scheduling
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All thread scheduling is down by the L4 kernel
The Linux server’s schedule() routine is only used for
multiplexing it’s single thread.
After each system call, if no other system call is pending,
it simply resumes the user process thread and sleeps.
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L4Linux – Design & Implementation
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Tagged TLB & Small Space.
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In order to reduce TLB conflicts, L4Linux has a special
library to customize code and data for communicating with
the Linux Server
The emulation library and signal thread are mapped close
to the application, instead of default high-memory area.
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Performance
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What is the penalty of using L4Linux?
Compare L4Linux to native Linux
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Does the performance of the underlying microkernel matter?
Compare L4Linux to MkLinux
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Does co-location improve performance?
Compare L4Linux to an in-kernel version of MkLinux
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Microbenchmarks
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measured system call
overhead on shortest
system call “getpid()”
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Microbenchmarks (cont.)
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Measures specific system calls to determine basic performance.
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Macrobenchmarks
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measured time to
recompile Linux server
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Macrobenchmarks (cont.)
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Next use a commercial test suite to simulate a system under full
load.
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Performance Analysis
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L4Linux is, on average 8.3% slower than native Linux.
Only 6.8% slower at maximum load.
MkLinux: 49% average, 60% at maximum.
Co-located MkLinux: 29% average, 37% at maximum.
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Extensibility Performance
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A micro-kernel must provide more than just the
features of the OS running on top of it.
Specialization – improved implementation of Os
functionality
Extensibility – permits implementation of new
services that cannot be easily added to a
conventional OS.
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Pipes and RPC
First five (1) use the standard pipe mechanism of the Linux kernel.
(2) Is asynchronous and uses only L4 IPC primitives. Emulates POSIX
standard pipes, without signalling. Added thread for buffering and crossaddress-space communication.
(3) Is synchronous and uses blocking IPC without buffering data.
(4) Maps pages into the receiver’s address space.
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Virtual Memory Operations
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The “Fault” operation is an example of extensibility – measures the time to resolve a
page fault by a user-defined pager in a separate address space.
“Trap” – Latency between a write operation to a protected page, and the invocation of
related exception handler.
“Appel1” – Time to access a random protected page. The fault handler unprotects the
page, protects some other page, and resumes.
“Appel2” – Time to access a random protected page where the fault handler only
unprotects the page and resumes.
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Conclusion
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Using the L4 micro-kernel imposes a 5-10% slowdown
to native Linux. Much faster than previous microkernels.
Further optimizations such as co-locating the Linux
Server, and providing extensibility could improve
L4Linux even further.
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