Transcript Lecture 17 Paging

Lecture 17
Paging
Hardware Support
Fall 2000
M.B. Ibáñez
Characteristics of
Paging and Segmentation
• Memory references are dynamically translated
into physical addresses at run time
– a process may be swapped in and out of main memory
such that it occupies different regions
• A process may be broken up into pieces that do
not need to located contiguously in main memory
– All pieces of a process do not need to be loaded in main
memory during execution
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Execution of a Program
• Operating system brings into main memory a few
pieces of the program
• Resident set - portion of process that is in main
memory
• An interrupt is generated when an address is
needed that is not in main memory
• Operating system places the process in a blocking
state
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Execution of a Program
• Piece of process that contains the logical
address is brought into main memory
– operating system issues a disk I/O Read request
– another process is dispatched to run while the
disk I/O takes place
– an interrupt is issued when disk I/O complete
which causes the operating system to place the
affected process in the Ready state
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Advantages of
Breaking up Process
• More processes may be maintained in main
memory
– only load in some of the pieces of each process
• With so many processes in main memory, it is
very likely a process will be in the Ready state at
any particular time
• It is possible for a process to be larger than all the
main memory
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Advantages of
Breaking up Processes
• Programmer is dealing with memory the
size of the hard disk
• It would be wasteful to load in many pieces
of the process when only a few pieces will
be used
• Time can be saved because unused pieces
are not swapped in and out of memory
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Types of Memory
• Real memory
– main memory
• Virtual memory
– memory on disk
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Principle of Locality
• Program and data references within a process tend
to cluster
• Only a few pieces of a process will be needed over
a short period of time
• Possible to make intelligent guesses about which
pieces will be needed in the future
• This suggests that virtual memory may work
efficiently
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Support Needed for
Virtual Memory
• Hardware must support paging and
segmentation
• Operating system must be able to
management the movement of pages and/or
segments between secondary memory and
main memory
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Paging
• Each process has its own page table
• Each page table entry contains the frame
number of the corresponding page in main
memory
• A bit is needed to indicate whether the page
is in main memory or not
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Paging
Virtual Address
Page
Number
Offset
Page Table Entry
P
M
Other Control
Bits
Frame Number
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Address Translation in a Paging System
Virtual Address
Page #
Offset
Frame #
Offset
Register
Page Table Ptr
Page Table
Offset
+
P#
Page
Frame
Frame #
Program
Paging
Main Memory
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Page Table
Implemented as a set of dedicated Registers
• These registers should be built with very
high-speed logic to make the paging address
translation efficient.
• DEC PDP-11 is an example of such
architecture. The address consists of 16 bits,
and the page size is 8K. The page table
consists of eight entries.
Fall 2000
M.B. Ibáñez
Page Table
Kept in Main Memory
• Two items:
– Page table in main memory
– page-table base register (PTBR) points to the page table
• Problem: access(location i):
– index into the page table using PTBR, we get the frame
number
– actual address = frame-number + page-offset
• Thus, memory access is slowed by factor of
2
Fall 2000
M.B. Ibáñez
Page Tables
• The entire page table may take up too much
main memory
• Page tables are also stored in virtual
memory
• When a process is running, part of its page
table is in main memory
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Translation Look-aside Buffer
(Associative Registers)
• Each virtual memory reference can cause
two physical memory accesses
– one to fetch the page table
– one to fetch the data
• To overcome this problem a special cache is
set up for page table entries
– called the TLB - Translation Look-aside Buffer
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Translation Look-aside Buffer
• Contains page table entries that have been
most recently used
• Works similar to main memory cache
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Translation Look-aside Buffer
• Given a virtual address, processor examines
the TLB
• If page table entry is present (a hit), the
frame number is retrieved and the real
address is formed
• If page table entry is not found in the TLB
(a miss), the page number is used to index
the process page table
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Translation Look-aside Buffer
• First checks if page is already in main
memory
– if not in main memory a page fault is issued
• The TLB is updated to include the new page
entry
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
Fall 2000
M.B. Ibáñez
Translation Look-aside Buffer
• Each register consists of two parts:
– A key
– A value
• When the associative registers are presented
with an item,
– it is compared with all the keys simultaneously
– If the item is found, the corresponding value
field is output
Fall 2000
M.B. Ibáñez
Use of a Translation Look-aside Buffer
Secondary
Memory
Main Memory
Virtual Address
Page # Offset
Translation
Lookaside Buffer
TLB hit
Offset
Load
page
Page Table
TLB miss
Frame # Offset
Real Address
Page fault
Fall 2000
From Operating Systems. Internals and Design Principles. W. Stalling. Prentice Hall.
M.B. Ibáñez
START
Operation of TLB
CPU checks
the TLB
Page
table entry in
TLB?
Yes
No
Access page
table
No
Page fault
handling routing
Fall 2000
Page in main
memory?
Yes
UpdateM.B.
TLBIbáñez
CPU generates
Physical
Address