Transcript CS350-08-paging+segmentation

Memory Management
Paging &Segmentation
CS311, CS350 & CS550
Implementation Issues in Paging
Four times when OS involved with paging
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Process creation
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Process execution
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MMU reset for new process
TLB flushed
Page fault time
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determine (virtual) address causing fault
swap target page out, needed page in
Process termination time
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determine program’s resident-set size
create page table
release page table, pages
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Page Fault Handling (1)
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Hardware traps to kernel, t1 is interrupted
Mode switch into kernel: Privilege mode ON, Interrupts
OFF, Protection OFF
General (users) registers saved
OS determines which (virtual) page needed
OS checks validity of (virtual) address
OS Seeks target/victim; if victim dirty, then write it to disk
OS schedules I/O request for new page from disk
OS dispatches another task (tn), while waiting
Page-in I/O completes, t2 registers saved
Page tables updated
Faulting instruction backed up to when it began
Faulting process scheduled
Registers restored
Program (t1) continues
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Locking Pages in Memory
(Virtual) memory and I/O occasionally interact
Proc issues call for read from device into buffer
while waiting for I/O, another processes starts up
has a page fault
buffer for the first proc may be chosen to be paged
out
Need to specify some pages locked
exempted from being target pages
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Separation of Policy and Mechanism
Page fault handling with an external pager
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Segmentation (Pt1)
 One-dimensional address space with growing tables
 One table may bump into another (solution?)
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Segmentation (Pt2)
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Allows each table to grow or shrink,
independently
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Segmentation (Pt3)
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Comparison of paging and segmentation
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Implementation of Pure Segmentation
(a)-(d) Development of checkerboarding (external fragmentation)
(e) Removal of the checkerboarding by compaction
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Segmentation with Paging: MULTICS (Pt1)
Descriptor segment
points to page tables
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Segment descriptor –
numbers are field
lengths
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Segmentation with Paging: MULTICS (Pt2)
Conversion of a 2-part MULTICS address into a main memory address
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Segmentation with Paging: Pentium (Pt1)
Similar to MULTICS, but addresses a number of different design goals
A Pentium
selector
GDT = Global Descriptor Table
LDT = Local Descriptor Table
 Code segment
descriptor
 Data segments
differ slightly
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Segmentation with Paging: Pentium (Pt2)
Conversion of a (selector, offset) pair to a linear address
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Segmentation with Paging: Pentium (Pt3)
Mapping of a linear address onto a physical address
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Segmentation with Paging: Pentium (Pt4)
Level
Protection on the Pentium
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References
 Chapters 8 and 9 :OS Concepts, Silberschatz, Galvin, Gagne
 Chapter 4: Modern Operating Systems, Andrew S. Tanenbaum
 X86 architecture
 http://en.wikipedia.org/wiki/Memory_segment
 Memory segment
 http://en.wikipedia.org/wiki/X86
 Memory model
 http://en.wikipedia.org/wiki/Memory_model
 IA-32 Intel Architecture Software Developer’s Manual, Volume
1: Basic Architecture
 http://www.intel.com/design/pentium4/manuals/index_new.htm
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