Transcript 2. Structs

Operating Systems
Certificate Program in Software Development
CSE-TC and CSIM, AIT
September -- November, 2003
2. Computer-System Structures
(Ch. 2, S&G)
 Objective
– to give a (selective) overview of
computer system architectures
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Contents
1. A Modern Computer System
2. Interrupts
3. I/O
4. Caching
5. Protection
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1. A Modern Computer System
Fig 2.1, p.24
Line Printer
CPU
disk
controller
printer
controller
tape-drive
controller
system bus
memory
controller
I/O controller
I/O controller
memory
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continued
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 CPU
and device controllers (drivers) can
execute concurrently.
 Access
to shared memory must be
controlled.
 A hard-wired
bootstrap program loads and
starts the OS kernel.
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2. Interrupts
 Modern
OSes are driven by interrupts
(traps) sent when events occur in hardware
or software.
 Types
of events:
– completion of I/O, division by 0, system calls,
etc.
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continued
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 An
interrupt causes the OS to stop its
current task, and switch execution to an
interrupt-processing routine.
 At
the end of the routine, the old task is
resumed
– the old task’s details must be stored during the
interrupt processing
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continued
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 The
addresses of the interrupt routines are
stored in a fixed segment of memory
(an interrupt vector).
 The
OS selects a routine from the interrupt
vector based on the ‘type’ of the interrupt it
received.
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continued
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 Features
of interrupts:
– disabling of other interrupts during interrupt
processing
– prioritisation
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System Calls
 System
Fig 2.9, p.44
calls are implemented using interrupts.
resident
monitor
1
trap to
monitor
case n
:
read
:
:
system call n
:
2
perform I/O
3 return
user program
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3. I/O
 Synchronous
I/O
– the user process waits during I/O processing
 Asynchronous
I/O
– control returns to the user without waiting for
the I/O to complete
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I/O Forms
Fig. 2.3, p.27
Synchronous
Asynchronous
user
user
requesting process
device driver
kernel
interrupt handler
hardware data
transfer
time
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requesting process
device driver
kernel
interrupt handler
hardware data
transfer
time
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3.1. Synchronous I/O
 Waiting
is done either with:
– a special wait instruction
– a busy-wait loop, such as:
loop: jmp loop
 A busy-wait
generates instruction fetches,
and so may lead to contention with the I/O.
 Only one I/O process involved.
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3.2. Asynchronous I/O
 Big
advantage: the CPU is not affected
while slow I/O is carried out.
 Many
I/O requests can be in action at once
– the implementation requires an I/O device
status table
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I/O Device Status Table
dev: card reader 1
status: idle
dev: line printer 3
status: busy
dev: disk unit 1
status: idle
dev: disk unit 2
status: idle
dev: disk unit 3
status: busy
:
:
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Fig 2.4, p.28
PID: 3445
addr: 34556
length: 1345
file: xxx
op: read
addr: 23456
length: 2000
file: yyy
op: write
addr: 6543
length: 500
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3.3. Direct Memory Access (DMA)
 Device
controllers transfer data blocks
to/from memory directly, bypassing the
CPU
– only one interrupt generated per block
– much faster than interrupt driven character
transfer
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3.4. Memory Mapped I/O
 I/O
device registers is mapped to memory
so that reads/writes to those memory
addresses go straight to the device
– used for fast and frequently used device
– e.g. video controller, serial port
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4. Caching
 The
cache is fast memory between the CPU
and main memory
– the CPU looks in the cache first for data
– new data taken from main memory is also
placed in the cache for quick access next time
 Instruction
caching
 Cache management
– can affect performance drastically
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Cache Coherency
 Must
ensure that the data in the cache is
always the same as its original version in
main memory.
 Complicated
by multiprocessor and
distributed environments
– several caches, replicated memory
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5. Protection
 5.1.
Dual-mode Operation
 5.2. Memory Protection
 5.3. CPU Protection
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5.1. Dual-mode Operation
 User
mode
 Monitor mode
– supervisor mode, root, superuser, system mode,
priveleged mode
 Implemented
in hardware
 OS always runs in monitor mode
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5.2. Memory Protection
 The
interrupt vector must be protected from
modification by users.
 The
interrupt processing routines must be
similarily protected.
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Partitioning Memory
Fig 2.7, p.40
0
monitor
256000
job 1
300040
job 2
300040
base register
420940
job3
120900
limit register
880000
job4
1024000
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Fig 2.8, p.41
 Only
addresses within the job’s memory
space are accessible.
base
CPU
address
>=
no
base + limit
yes
<
no
yes
memory
trap to OS monitor -- addressing error
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5.3. CPU Protection
 Each
process is interrupted after a fixed
time
– this breaks infinite loops in poor code which
would otherwise hog the CPU
– allows the OS to time-slice users by context
switching
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