Transcript CS350-09-1-DJ-mem-mgt

Memory Management
Adapted From Modern Operating Systems, Andrew S. Tanenbaum
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Memory Management
• Ideally programmers want memory that is
– large
– fast
– non volatile
• Memory hierarchy
– small amount of fast, expensive memory – cache
– some medium-speed, medium price main memory
– gigabytes of slow, cheap disk storage
• Memory manager handles the memory hierarchy
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Basic Memory Management
Monoprogramming without Swapping or Paging
Three simple ways of organizing memory
(in an operating system with one user process)
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Multiprogramming with Fixed Partitions
• Fixed memory partitions
– separate input queues for each partition
– single input queue
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Relocation and Protection
• Cannot be sure where program will be loaded in memory
– address locations of variables, code routines cannot be absolute
(see next slide)
– must keep a program out of other processes’ partitions
• Use base and limit values
– address locations added to base value to map to physical addr
– address locations larger than limit value is an error
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Seeing the problem
extern int x; // placement determined by loader
void Fcn (void){int y;
x=x+1;}
Compiles to:
Compiled address
(in 32-bit words)
instruction
[0]
define storage for x – outside program
0
[function initialization (10 words)]
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load address of x
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load x
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add 1 to x
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store result
but where is x at runtime?
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Swapping (1)
Memory allocation changes as
– processes come into memory
– leave memory
Shaded regions are unused memory
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Swapping (2)
a. Allocating space for growing data segment
b. Allocating space for growing stack & data segment
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Page Replacement Algorithms (1)
• Page fault forces choice
– which page must be removed (the “victim”)
• Modified page must first be saved
– unmodified just overwritten
• Better not to choose an often used page
– will probably need to be brought back in soon
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Page Replacement Algorithms (2)
• Optimal Page Replacement
– Replace page needed at the
farthest point in future
– Optimal but unrealizable
(Why?)
• FIFO
• Not Recently Used (NRU)
• Clock
• Second Chance
• Least Recently Used (LRU)
rarely implemented - why?
• Not Frequently Used (NFU)
• Aging
• Working Set
• WSClock
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Design Issues for Paging Systems
Local versus Global Allocation Policies
• Original
• Local page
configuration
replacement
• Global page
replacement
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Virtual Memory
Paging (1)
The position and function of the MMU
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Paging (2)
The relation between
virtual addresses
and physical
memory addresses given by
page table
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Page Tables (1)
15 bits for real
address
214+213=
16384+ 8192=24576
24576+4=24580
Remaining 8 pages
not mapped
16-bit vaddr
Internal operation of MMU with 16 4 KB pages
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Page Tables (2)
Second-level page tables
Top-level
page table
• 32 bit address with 2 page
table fields
• 8 bytes/entry
• OK for 32-bit machine
• 64-bit machine needs 252
entries >30GB
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Page Tables (3)
Typical page table entry
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TLBs – Translation Lookaside Buffers
A TLB to speed up paging
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3 table schemes
See cs350-10+11
Inverted table
1 entry/page
in memory
PID+V. Page#
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Problem with IPT’s
• Virtual-real translation harder
• Cannot use virtpg# as index
– must search entire table
– On EVERY reference
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Cleaning Policy
• Need for a background process, paging daemon
– periodically inspects state of memory
• When too few page frames are free
– selects pages to evict using a replacement algorithm
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Load Control
• Despite good designs, system may still thrash when
– some processes need more memory
– but no processes need less
• Solution :
Reduce number of processes competing for memory
– swap one or more to disk, divide up pages they held
– reconsider degree of multiprogramming
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Page Size
Small page size
• Advantages
– less internal fragmentation
– better fit for various data structures, code sections
• Disadvantages
– program needs more pages has larger page table
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Separate Instruction and Data Spaces
• One address space
• Separate I and D spaces
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Shared Pages
Two processes sharing same program sharing its page table
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References
• Chapters 8 and 9 :OS Concepts, Silberschatz, Galvin, Gagne
• Chapter 4: Modern Operating Systems, Andrew S. Tanenbaum
• X86 architecture
– http://en.wikipedia.org/wiki/X86
• Memory segment
– http://en.wikipedia.org/wiki/Memory_segment
• Memory model
– http://en.wikipedia.org/wiki/Memory_model
• IA-32 Intel Architecture Software Developer’s Manual, Volume 1:
Basic Architecture
– http://www.intel.com/design/pentium4/manuals/index_new.htm
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