Transcript Pengantar Organisasi Komputer

IKI10230
Pengantar Organisasi Komputer
Bab 4.1: Input/Output & Interrupt
Sumber:
1. Hamacher. Computer Organization, ed-5.
2. Materi kuliah CS152/1997, UCB.
19 Maret 2003
Bobby Nazief ([email protected])
Qonita Shahab ([email protected])
bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/
1
Input/Output: Gerbang Ke Dunia Luar
Devices
Keyboard,
Mouse
Input
Disk
Computer
Processor
(active)
Control
(“brain”)
Datapath
(“brawn”)
Memory
(passive)
(where
programs,
data
live when
running)
Output
(where
programs,
data
live when
not running)
Display,
Printer
2
Motivation for Input/Output
° I/O is how humans interact with
computers
° I/O lets computers do amazing things:
• Read pressure of synthetic hand and control
synthetic arm and hand of fireman
• Control propellers, fins, communicate
in BOB (Breathable Observable Bubble)
• Read bar codes of items in refrigerator
° Computer without I/O like a car without
wheels; great technology, but won’t get
you anywhere
3
I/O Device Examples and Speed
° I/O Speed: bytes transferred per second
(from mouse to display: million-to-1)
° Device
Behavior
Partner
Keyboard
Mouse
Line Printer
Floppy disk
Laser Printer
Magnetic Disk
Network-LAN
Graphics Display
Input
Input
Output
Storage
Output
Storage
I or O
Output
Human
Human
Human
Machine
Human
Machine
Machine
Human
Data Rate
(Kbytes/sec)
0.01
0.02
1.00
50.00
100.00
10,000.00
10,000.00
30,000.00
4
What do we need to make I/O work?
° A way to connect many types of
devices to the Proc-Mem
Files
Windows
° A way to control these devices, Operating System
respond to them, and transfer
data
° A way to present them to user
programs so they are useful
Proc
Mem
PCI Bus
SCSI Bus
cmd reg.
data reg.
5
Organisasi I/O
Prosesor
Memori
°°°
Control Lines
Address Lines
Data Lines
Address
Decoder
Control
Circuits
Data & Status
Registers
BUS
I/O Interface
Input Device
6
A Bus is:
° shared communication link
° single set of wires used to connect multiple
subsystems
Processor
Input
Control
Memory
Datapath
Output
7
Review: Organisasi Input/Output
Bus
Prosesor
DATAIN
DATAOUT
SIN
SOUT
Keyboard
Display
° I/O Device biasanya memiliki 2 register:
• 1 register menyatakan kesiapan untuk menerima/mengirim data
(I/O ready), sering disebut Status/Control Register  SIN, SOUT
• 1 register berisi data, sering disebut Data Register  DATAIN, DATAOUT
° Prosesor membaca isi Status Register terus-menerus, menunggu
I/O device men-set Bit Ready di Status Register (0  1)
° Prosesor kemudian menulis atau membaca data ke/dari Data
Register
• tulis/baca ini akan me-reset Bit Ready (1  0) di Status Register
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Review: Contoh Program Input/Output
° Input: Read from keyboard
READ:
Move
TestBit
Branch=0
Move
#LOC,R0
#3,INSTATUS
READ
DATAIN,(R0)
;
;
;
;
Initialize memory
Keyboard (IN) ready?
Wait for key-in
Read character
#3,OUTSTATUS;
ECHO
;
(R0),DATAOUT;
#CR,(R0)+
;
;
Branch≠0 READ
;
Call
Process
;
Display (OUT) ready?
Wait for it
Write character
Is it CR?
Meanwhile, stores it
No, get more
Do something
° Output: Write to display
ECHO:
TestBit
Branch=0
Move
Compare
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Memory-mapped-I/O vs. I/O-mapped-I/O
° Status & Data Registers are treated as memory
locations:
• Called “Memory Mapped Input/Output”
• A portion of the address space dedicated to communication
paths to Input or Output devices (no memory there)
• The registers are accessed by Load/Store instructions, just like
memory
° Some machines have special input and output
instructions that read-from and write-to Device
Address Space:
• Called “I/O Mapped Input/Output”
• IN Rx,Device-Address
; Processor  Device
; Rx  Rdevice-Address
• OUT Device-Address,Rx
; Device  Processor
; Rdevice-Address  Rx
10
Contoh Program Input/Output (I/O-mapped-I/O)
° Input: Read from keyboard
READ:
Move
In
TestBit
Branch=0
In
Move
#LOC,R0
INSTATUS,R1
#3,R1
READ
DATAIN,R1
R1,(R0)
;
;
;
;
;
;
Initialize memory
Read status
Keyboard (IN) ready?
Wait for key-in
Read character
Store in memory
OUTSTATUS,R1;
#3,R1
;
ECHO
;
(R0),R1
;
R1,DATAOUT ;
#CR,(R0)+
;
;
Branch≠0 READ
;
Call
Process
;
Read status
Display (OUT) ready?
Wait for it
Get the character
Write it
Is it CR?
Meanwhile, stores it
No, get more
Do something
° Output: Write to display
ECHO:
In
TestBit
Branch=0
Move
Out
Compare
11
Polling
12
Processor-I/O Speed Mismatch
° 500 MHz microprocessor can execute 500 million
load or store instructions per second, or 2,000,000
KB/s data rate
• I/O devices from 0.01 KB/s to 30,000 KB/s
° Input: device may not be ready to send data as fast
as the processor loads it
• Also, might be waiting for human to act
° Output: device may not be ready to accept data as
fast as processor stores it
° What to do?
13
Program-Controlled I/O: Polling
OUT
IN
DATAIN
STATUS
DATAOUT
° Input: Read from keyboard
WAITK:
Move
TestBit
Branch=0
Move
R1,#line
STATUS,#0
WAITK
R0,DATAIN
° Output: Write to display
WAITD:
TestBit
Branch=0
Move
Move
Compare
Branch≠0
Call
STATUS,#1
WAITD
DATAOUT,R0
(R1)+,R0
R0,#$0D
WAITK
Process
;
;
;
;
Initialize memory
Keyboard (IN) ready?
Wait for key-in
Read character
;
;
;
;
;
;
;
Display (OUT) ready?
Wait for it
Write character
Store & advance
Is it CR?
No, get more
Do something
° Processor waiting for I/O called “Polling”
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Cost of Polling?
° Assume for a processor with a 500-MHz clock it takes
400 clock cycles for a polling operation (call polling
routine, accessing the device, and returning).
Determine % of processor time for polling
• Mouse: polled 30 times/sec so as not to miss user movement
• Floppy disk: transfers data in 2-byte units and has a data rate of 50
KB/second.
No data transfer can be missed.
• Hard disk: transfers data in 16-byte chunks and can transfer at 8
MB/second. Again, no transfer can be missed.
15
% Processor time to poll mouse, floppy
° Times Mouse Polling/sec
= 30 polls/sec
° Mouse Polling Clocks/sec
= 30 * 400 = 12000 clocks/sec
° % Processor for polling:
12*103/500*106 = 0.002%
 Polling mouse little impact on processor
° Times Polling Floppy/sec
= 50 KB/s /2B = 25K polls/sec
° Floppy Polling Clocks/sec
= 25K * 400 = 10,000,000 clocks/sec
° % Processor for polling:
10*106/500*106 = 2%
 OK if not too many I/O devices
16
% Processor time to hard disk
° Times Polling Disk/sec
= 8 MB/s /16B = 500K polls/sec
° Disk Polling Clocks/sec
= 500K * 400 = 200,000,000 clocks/sec
° % Processor for polling:
200*106/500*106 = 40%
 Unacceptable
17
Interrupt
18
What is the alternative to polling?
° Wasteful to have processor spend most of its time
“spin-waiting” for I/O to be ready
° Wish we could have an unplanned procedure call
that would be invoked only when I/O device is
ready
° Solution: use interrupt mechanism to help I/O.
Interrupt program when I/O ready, return when
done with data transfer
19
I/O Interrupt
° An I/O interrupt is like a subroutine call except:
• An I/O interrupt is “asynchronous”
• More information needs to be conveyed
° An I/O interrupt is asynchronous with respect to
instruction execution:
• I/O interrupt is not associated with any instruction, but it can
happen in the middle of any given instruction
• I/O interrupt does not prevent any instruction from completion
20
Interrupt Driven Data Transfer
Memory
(1) I/O
interrupt
add
sub
and
or
(2) save PC
user
program
(3) interrupt
service addr (4)
read
store
(5) ...
jr
interrupt
service
routine
21
Interrupt Service Routine (Interrupt Handler)
Main Program
Move
#Line,PNTR
; Initialize buffer pointer.
Clear
EOL
; Clear end-of-line indicator.
BitSet
#2,CONTROL
; Enable keyboard interrupts.
BitSet
#9,PS
; Set interrupt-enable bit in the PS.
…
Interrupt Service Routine
Read:
MoveMultiple
RO-R1,-(SP)
; Save R0 & R1 on stack.
Move
PNTR,R0
; Load buffer pointer.
MoveByte
DATAIN,R1
; Get input character and
MoveByte
R1,(R0)+
; store it in the buffer.
Move
R0,PNTR
; Update buffer pointer.
CompareByte
#$0D,R1
; Check if Carriage Return
Branch≠0
RTRN
Move
#1,EOL
; Indicate end-of-line.
BitClear
#2,CONTROL
; Disable keyboard interrupts.
(SP)+,RO-R1
; Restore R0 & R1.
RTRN:
MoveMultiple
Return-from-interrupt
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Benefit of Interrupt-Driven I/O
° 400 clock cycle overhead for each transfer, including
interrupt. Find the % of processor consumed if the
hard disk is only active 5% of the time.
° Interrupt rate = polling rate
• Disk Interrupts/sec = 8 MB/s /16B
= 500K interrupts/sec
• Disk Transfer Clocks/sec = 500K * 400
= 200,000,000 clocks/sec
• % Processor for during transfer: 250*106/500*106= 40%
° Disk active 5%  5% * 40%  2% busy
Determined by disk’s activity, whereas in Pollingdriven I/O the Processor will be busy polling 40% of
the time even if the disk is not active
23
Instruction Set Support for I/O Interrupt
° Save the PC for return
• To enable the “proper return” when the interrupt has been served
• AVR uses the stacks
° Where to go when interrupt occurs?
• To allow “proper branch” to the service routine
• AVR defines:
- Locations 0x000 – 0x002 for external interrupts
-
Locations 0x003 – 0x00C for internal interrupts
° Determine cause of interrupt?
• To guarantee “proper service routine” serving “proper interrupt”
• AVR uses vectored interrupt, which associates the location of the
interrupt service routine (see above) with the device that causes it
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Interrupt Hardware
25
Interrupt Request
Vdd
INTR
Processor
INTR1
INTR2
INTRn
° I/O Devices interrupt processor through a single
line known as Interrupt Request signal (INTR)
° To serve n devices, the line uses wired-or
connection that allows any interrupting device to
activate the signal
• any INTRi is switched on, INTR will become TRUE
26
Sequence of Events during Interrupt
1. The device activates interrupt request signal.
2. The processor interrupts the program currently
being executed.
3. Interrupts are disabled by changing the control
bits in the PS.
4. The device is informed that its request has been
recognized, and in response, it deactivates the
interrupt request signal.
5. The action requested by the interrupt is
performed by the interrupt service routine.
6. Interrupts are enabled and execution of the
interrupted program is resumed.
27
Multiple Devices/Interrupts
° How to handle simultaneous interrupt requests?
• Need to have priority scheme
° Which I/O device caused exception?
• Need to convey the identity of the device generating the interrupt
° Can processor avoid interrupts during the interrupt
routine?
• In general, interrupts are disabled whenever one is being serviced;
interrupts will be enabled after the service is completed
• However, occasionally a more important interrupt may occur while
this interrupt being served
° Who keeps track of status of all the devices, handle
errors, know where to put/supply the I/O data?
• In general, these is one of the tasks of Operating System
28
Device Identification
Device 1
CPU
INTR1
Device 2
INTR2
Device N
INTRn
wired-OR
° The Interrupting Device may provide its identity
through:
• Interrupt-Request (IRQ) bit in its Status Register, which will be
evaluated one-by-one by the processor (polling)
• Sending special code the the processor over the bus (vectored
interrupt)
29
Prioritized Interrupt: Daisy Chain Scheme
Device 1
Highest
Priority
Device N
Lowest
Priority
Device 2
INTA
CPU
Release
INTR
wired-OR
° Advantage: simple
° Disadvantages:
• Cannot assure fairness:
A low-priority device may be locked out indefinitely
30
Prioritized Interrupt: Priority Groups
Device 1
Device 2
Device N
INTA1
INTR1
CPU
INTA2
INTR2
° Interrupt Nesting: an Interrupt Service Routine may
be interrupted by other, higher-priority interrupt
31
Exceptions
32
Exceptions
° Interrupt is only a subset of Exception
• Exception: signal marking that something “out of the ordinary”
has happened and needs to be handled
° Interrupt: asynchronous exception
• Unrelated with instruction being executed
° Trap: synchronous exception
•
•
•
•
Related with instruction being executed
To recover from errors: Illegal Instruction, Divide By Zero, …
To debug a program
To provide privilege (for Operating System)
33
I/O & Operating System
° The I/O system is shared by multiple programs using the
processor
• OS guarantees that user’s program accesses only the portions
of I/O device to which user has rights (e.g., file access)
° Low-level control of I/O device is complex because requires
managing a set of concurrent events and because
requirements for correct device control are often very detailed
• OS provides abstractions for accessing devices by supplying
routines that handle low-level device operations
° I/O systems often use interrupts to communicate information
about I/O operations
• OS handles the exceptions generated by I/O devices (and
arithmetic exceptions generated by a program)
° Would like I/O services for all user programs under safe
control
• OS tries to provide equitable access to the shared I/O resources,
as well as schedule accesses in order to enhance system
performance
34
I/O – OS – User’s Program
User’s
Program
getchar(); System.in.readLine();
putchar(); System.out.println();
I/O
Services
Device
Driver
Device
Driver
Device
Driver
OS
I/O Device
35
OS Interrupt Services
OSINIT
Set interrupt vectors
Time-slice clock  SCHEDULER
Trap  OSSERVICES
VDT interrupts  IODATA
SCHEDULER
OSSERVICES
IODATA
…
…
OSSERVICES Examine stack to determine requested operation
Call appropriate routine
PC
SCHEDULER Save current context
Select a runnable process
Restore saved context of new process
Push new values for PS and PC on stack
Return from interrupt
36
I/O ROUTINES & DEVICE DRIVER
IOINIT
Set process status to Blocked
Initialize memory buffer address pointer
Call device driver to initialize device & enable
interrupts in the device interface (VDTINIT)
Return from subroutine
IODATA
Poll devices to determine source of interrupt
Call appropriate device driver (VDTDATA)
If END = 1, then set process status to Runnable
Return from interrupt
VDTINIT
Initialize device interface
Enable interrupts
Return from subroutine
VDTDATA
Check device status
If ready, then transfer character
If character = CR, then set END = 1;
else set END = 0
Return from subroutine
37
Contoh: Main Program
.cseg
.org INT0addr
rjmp ext_int0
.org OVF0addr
rjmp tim0_ovf
main:
Do some initializations
rcall uart_init
sei
idle:
sbrs u_status,RDR
rjmp idle
Do the work
wait:
sbrc u_status,TD
rjmp wait
Wrap it up
;External interrupt handler
;Timer0 overflow handler
;Init UART
;Enable interrupts
;Wait for Character
;Wait until data is sent
38
Contoh: Interrupt Handler
ext_int0:
ldi
u_status,1<<BUSY ;Set busy-flag (clear all others)
Do some work
ldi
u_tmp,1<<TOIE0 ;Set bit 1 in u_tmp
out
TIFR,u_tmp
; to clear T/C0 overflow flag
out
TIMSK,u_tmp
; and enable T/C0 overflow interrupt
Do more work
clr
u_bit_cnt
;Clear bit counter
out
GIMSK,u_bit_cnt ;Disable external interrupt
reti
tim0_ovf:
sbrs u_status,TD
;if transmit-bit set
Do something
ldi
u_tmp,1<<INT0
;(u_bit_cnt==9):
out
GIMSK,u_tmp
;Enable external interrupt
clr
u_tmp
out
TIMSK,u_tmp
;Disable timer interrupt
cbr
u_status,(1<<BUSY)|(1<<TD) ;Clear busy-flag and transmit-flag
reti
39