Transcript FPGA - המחלקה להנדסת חשמל ומחשבים

DE1 FPGA board and
Quartus
CPU Architecture
Objectives
The FPGA board
Using Quartus
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Coding
Compiling
Simulating
Pin Assignment
Configuring the board
Debugging
PLLs and Templates
Altera DE1 FPGA Board
Cyclone II EP2C20F484C6 FPGA
512KB SRAM , 8MB SDRAM ,4MB Flash
50MHz,27MHz and 24MHz oscillators for clock sources
SD Card socket
4 pushbutton switches
10 toggle switches
10 red and 8 Green LEDs
24-bit audio CODEC
VGA DAC
RS-232 interface
PS/2 mouse/keyboard Interface
Two 40-pin Expansion Headers
DE1 board description
Quartus II
Synthesis tool
Place and Route
Simulator
Debugger
Programmer
And much more
Example application
32bit behavioral counter with enable
8 MSB connected to green LEDs
Enable connected to switch
Clock to 50MHz onboard oscillator
Example Code
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is port (
clk,enable : in std_logic;
q
: out std_logic_vector (7 downto 0));
end entity;
architecture rtl of counter is
signal q_int : std_logic_vector (31 downto 0);
begin
process (clk)
begin
if (rising_edge(clk)) then
if enable = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
q <= q_int(31 downto 24); -- Output only 8MSB
end rtl;
Project Files description
.qpf Project file
.qsf Settings file (timing , constrains , pin)
.vhd Design file , must be at least a top
level design file , its ports are directly
connected to physical pins
.stp Signal Tap file
.vwf Simulation Waveform file
.sof FPGA programming file
What is a Top Level
Serves as a top level hierarchy
Connects to FPGA physical pins
All the I/Os are routed through it
Entity 1
Entity 2
FPGA
Pins
Top Level
Entity 3
FPGA
Starting New Project
Open Quartus II (7.2)
Start Wizard File->New Project Wizard
Click Next , Specify Name of Project and the
directory and click Next
Specify files you want to add and click Next
Specify FPGA and click Next , Next and
Finish
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Cyclone II , EP2C20F484C6
Turn off Incremental Compilation
Assignments->Settings->Compilation Process
Settings -> Incremental Compilation
Operating VHDL Files
Create new files File->New
Add existing files and set compilation order
Assignments ->Settings->Files
Changing Top level entity
Assignments->General ->Top-level entity
Analyze the project : Push
Button
View resource utilization at “Compilation Report”
Viewing Synthesis results
RTL Synthesis
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Tools -> Netlist Viewers -> RTL viewer
Add0
cnt[31..0]
PRE
A[31..0]
32' h00000001 --
OUT[31..0]
D
Q
B[31..0]
q[7..0]
ENA
ADDER
CLR
clk
enable
Technology Synthesis
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Tools -> Netlist Viewers -> Technology map viewer
Setting Simulation
Add Vector file File->New
Add signals Edit->Insert->Insert node or bus
Press the “Node Finder” and select signals
Change Simulation Time Edit->End Time, Edit>Grid Size
Setting waveforms
Use the buttons on the left side to
generate input signals
Running simulation
Save the Waveform file and go to :
Assignments-> Settings->Simulator settings
Set simulation mode to Functional and choose your file
as simulation input
Ctrl+Shift+K – Starts the simulation
Look on The simulation report
Setting clock constrains
Open Settings : Assignments -> Settings->Timing
Analyzer Settings -> Classic timing analyzer settings
Press “Individual clocks” button
Setting clock constrains
Click New
At the end press OK
Specify Some Name
Select Input
Set Frequency
Manual Pin Assignments
Open Pin Planner (Assignments -> Pins)
Specify Pin Numbers
according to DE1 Data
book with PIN_ prefix
Automatic CSV pin Assignment
Uses CSV file from manufacturer
Top level names must be according to CSV file
Open : Assignments -> Import Assignments
Select CSV File
Press OK
Full compilation
Press
Button
After compilation open timing analyzer in
compilation report and see that all timings are OK.
Programming the FPGA
Connect the DE1 board to power
Connect DE1 board to PC using USB cable
Power on the board using RED button
Push the programmer button
in Quartus
Programming the FPGA - cont
Push Hardware Setup and Select USB-Blaster
Push the Auto Detect button
Then double click the <none> and select sof
Check the “Program configure” box
Push Start button
SignalTAP logic analyzer
A SignalTAP logic analyzer is used for
debugging of FPGA logic.
Do not require huge and expensive
equipment
No massive external connections needed
Captures internal FPGA signals using a
defined clock signal
Uses FPGA resources
Logic Analyzer - How it works
Like a Pipe with water with faucet (trigger)
Water are getting in all the time (data)
trigger
Samples Captured
Samples Captured
Old Samples
New Samples
TIME
When trigger occurs faucet closes (capture stops),
and you can see what is in the pipe
Trigger Options
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Pre Trigger
Center Trigger
Post Trigger
Signal TAP - How it Works
Signal Tap “Wastes” FPGA Logic
Quartus II
USB
JTAG
Interface
Memory
Signal Tap
Logic
Trigger Logic
User Signals
FPGA
Activating STP in Web Eddition
Go to : Options -> Internet Connectivity ->
TalkBack Options
Signal TAP Usage
Create .STP File
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Assign Sample Clock
Specify Sample Depth
Assign Signals to STP File
Specify Triggering
Setup JTAG
Save .STP File & Compile with Design
Program Device
Acquire Data
Create new STP File
Method 1
 Select the
in Quartus II
Method 2
 Select New (File Menu)
 Other Files
 SignalTap II File
STP Componnents
JTAG Chain
Configuration
Instance Manager
Waveform Viewer
Signal Configuration
STP Setup
Select USB-Blaster
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In JTAG Configuration
Set Sample Clock
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Use Global Clock
Every Sample taken at Clock Rising Edge
Cannot Be Monitored as Data
Specify Sample Depth
Set Trigger mode
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Sequential
Specify Trigger Position
Pre , Center , Post
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Select Number of trigger conditions
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Adding Signals
Select “Setup” tab and add signals (double click)
Setting Triggers
All signals must satisfy trigger condition to cause
data capture
Right-Click
to Set Value
STP Compilation
Save The STP file
Open Assignments  Settings
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Specify the STP File to Compile with Project
Run Full Project Compilation and reprogram
FPGA
Acquiring Data
Signal Tap II Toolbar & STP File Controls
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Run
Autorun
Stop
Templates
While in VHD file push
button on the left
In a template window select the needed logic
template
PLL
Open MegaWisard Tools->MegaWisard Plug in manager
and click Next
Select VHDL
Open I/O
Set Name
Select
ALTPLL
Click Next
Practice
Build a 8 bit circular Shift Register with
enable
Make all the Quartus process as with
counter
Working At Home
You can download a Quartus Web edition
version from
https://www.altera.com/support/software/download/
sof-download_center.html
References
Quartus user manual
DE1 board data sheet
Altera web site.
Cyclone II Data sheet
Any questions?