Transcript Input / Output

Input / Output
Tanenbaum Chapter 5
Silberschatz – Ch 12, 13
I/O Hardware
• Human readable
–
–
–
–
used to communicate with the user
video display terminals
keyboard, mouse
printer
• Machine readable
–
–
–
–
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used to communicate with electronic equipment
disk drives, tape drives, modems
serial, parallel, network ports
controllers
2
Differences Among I/O Devices
• Data Transfer Rate
• Application
– disk used to store files / disk used to store virtual
memory pages
•
•
•
•
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Complexity of control
Unit of transfer
Data representation (encoding schemes)
Error conditions (devices respond to errors
differently)
3
I/O Devices
Figure 5-1. Some
typical device,
network, and bus
data rates.
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I/O Hardware Concepts
• Bus (shared direct access or daisy chain)
CPU
monitor
graphics
controller
IDE disk
controller
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cache
bridge
controller
memory
PCI Bus
expansion
bus
scsi
controller
keyboard
serial port
5
I/O Hardware Concepts
• Bus (shared direct access or daisy chain)
• Port
CPU
monitor
graphics
controller
IDE disk
controller
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cache
bridge
controller
memory
PCI Bus
expansion
bus
scsi
controller
keyboard
serial port
6
I/O Hardware Concepts
• Bus (shared direct access or daisy chain)
• Port
• Controller
CPU
monitor
graphics
controller
IDE disk
controller
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cache
bridge
controller
memory
PCI Bus
expansion
bus
scsi
controller
keyboard
serial port
7
Application I/O Interface
• Objective of the I/O system is to encapsulate
individual device behaviors in generic classes.
• The device driver layer hides the differences
among I/O controllers from the kernel
• Devices vary in many dimensions
–
–
–
–
–
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Character-stream vs Block devices
Sequential vs Random-access location
Synchronous vs Asynchronous data transfer
Sharable vs Dedicated I/O device
Read, Write, or Read/Write
8
Kernel I/O Structure
Device Drivers
kernel
Kernel I/O Subsystem
SCSI keyboard mouse
device device device
driver driver driver
SCSI keyboard mouse
device device device
contrlr contrlr contrlr
SCSI
keyboard mouse
device
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...
PCI bus
device
driver
floppy
device
driver
ATAPI
device
driver
...
PCI bus floppy
device device
contrlr contrlr
ATAPI
device
contrlr
...
PCI bus
floppy
drive
ATAPI
devices
9
Software I/O Techniques
• Polling (programmed I/O)
– send command and wait
• Interrupt Driven I/O
– send command and continue
• Direct Memory Access (DMA)
– Use separate processor to manage I/O
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Polling
• CPU determines state of I/O device
– Status register
• To send data to I/O device:
– Host reads busy bit until clear.
– Host sets write bit and sends data to data-out
register
– Host sets command-ready bit
– Controller sets busy bit
– Controller reads command register and sees write
command
– Controller reads data in data-out register and
clears command-ready, error, and busy when
complete
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Programmed I/O (1)
Figure 5-7. Steps in printing a string.
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Programmed I/O (2)
Figure 5-8. Writing a string to the printer using programmed I/O.
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Interrupt Driven I/O
• Interrupts are handled through an interrupt
controller
• Types of interrupts
– nonmaskable - invalid address, divide by zero, etc
– maskable - device controllers
• Identification of interrupts
– Interrupt vector: Addresses of each interrupt
handling routine.
– Interrupt priority implicit in vector
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Interrupt Driven I/O
device driver
initiates I/O
Receives Int.,
transfers to Int
handler
initiates I/O
when complete,
generates int.
Int. handler
processes data
resume processing
of interrupted task
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CPU
I/O Controller
15
Interrupt Driven I/O
device driver
initiates I/O
Receives Int.,
transfers to Int
handler
initiates I/O
when complete,
generates int.
Int. handler
processes data
resume processing
of interrupted task
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CPU
I/O Controller
16
Interrupt Driven I/O
device driver
initiates I/O
Receives Int.,
transfers to Int
handler
initiates I/O
when complete,
generates int.
Int. handler
processes data
resume processing
of interrupted task
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CPU
I/O Controller
17
Interrupt Driven I/O
device driver
initiates I/O
Receives Int.,
transfers to Int
handler
initiates I/O
when complete,
generates int.
Int. handler
processes data
resume processing
of interrupted task
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CPU
I/O Controller
18
Interrupt Driven I/O
device driver
initiates I/O
Receives Int.,
transfers to Int
handler
initiates I/O
when complete,
generates int.
Int. handler
processes data
resume processing
of interrupted task
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CPU
I/O Controller
19
Interrupt Driven I/O
device driver
initiates I/O
Receives Int.,
transfers to Int
handler
initiates I/O
when complete,
generates int.
Int. handler
processes data
resume processing
of interrupted task
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CPU
I/O Controller
20
Interrupt Handlers (1)
1. Save registers not already been saved by
interrupt hardware.
2. Set up a context for the interrupt service
procedure.
3. Set up a stack for the interrupt service
procedure.
4. Acknowledge the interrupt controller. If there is
no centralized interrupt controller, reenable
interrupts.
5. Copy the registers from where they were saved
to the process table.
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Interrupt Handlers (2)
6. Run the interrupt service procedure.
7. Choose which process to run next.
8. Set up the MMU context for the process to
run next.
9. Load the new process’ registers, including its
PSW.
10. Start running the new process.
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Direct Memory Access
• Takes control of the system from the CPU to
transfer data to and from memory over the
system bus
• Cycle stealing is used to transfer data on the
system bus
• The instruction cycle is suspended so data
can be transferred
• The CPU pauses one bus cycle
• No interrupts occur
– No need to save context
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DMA Transfer Process
Device driver gets command to transfer data (C bytes)
from disk to memory buffer (address X)
processor
monitor
graphics
controller
DMA
IDE disk
controller
disk
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memory
PCI Bus
expansion
bus
scsi
controller
keyboard
serial port
disk
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DMA System Architecture
Device driver instructs disk controller to
transfer data from disk to buffer in memory
processor
monitor
graphics
controller
DMA
IDE disk
controller
disk
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memory
PCI Bus
expansion
bus
scsi
controller
keyboard
serial port
disk
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DMA System Architecture
Disk controller initiates DMA transfer
processor
monitor
graphics
controller
DMA
IDE disk
controller
disk
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memory
PCI Bus
expansion
bus
scsi
controller
keyboard
serial port
disk
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DMA System Architecture
Disk controller sends each byte to DMA controller
processor
monitor
graphics
controller
DMA
IDE disk
controller
disk
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memory
PCI Bus
expansion
bus
scsi
controller
keyboard
serial port
disk
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DMA System Architecture
DMA controller transfers data to memory,
adjusting addresses and sizes accordingly
processor
monitor
graphics
controller
DMA
IDE disk
controller
disk
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memory
PCI Bus
expansion
bus
scsi
controller
keyboard
serial port
disk
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DMA System Architecture
When C = 0, DMA interrupts to signal
completion of DMA transfer
processor
monitor
graphics
controller
DMA
IDE disk
controller
disk
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memory
PCI Bus
expansion
bus
scsi
controller
keyboard
serial port
disk
29
Typical DMA Block Diagram
The processor identifies whether a read or write is requested,
and loads starting memory address, byte count, I/O address
Data
Count
Data Lines
Data
Register
Address Lines
Address
Register
DMA Request
DMA Acknowledge
Interrupt
Control
Logic
Read
Write
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Typical DMA Block Diagram
I/O device initiates DMA Request. DMA controller seizes
memory bus, returns ACK. I/O sends data thru DMA
Data
Count
Data Lines
Address Lines
Data
Register
Address
Register
DMA Request
DMA Acknowledge
Interrupt
Control
Logic
Read
Write
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Typical DMA Block Diagram
When data transfer is complete, DMA signals with interrupt
Data
Count
Data Lines
Data
Register
Address Lines
Address
Register
DMA Request
DMA Acknowledge
Interrupt
Control
Logic
Read
Write
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DMA Transfer Process
• Device driver gets command to transfer data (C bytes)
from disk to memory buffer (address X)
• Device driver instructs disk controller to transfer data from
disk to buffer in memory
• Disk controller initiates DMA transfer
• Disk controller sends each byte to DMA controller
• DMA controller transfers data to memory, adjusting
addresses and sizes accordingly
• When C = 0, DMA interrupts to signal completion of DMA
transfer
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DMA / Interrupt Breakpoints
Time
Instruction Cycle
Processor
Cycle
Processor
Cycle
Processor Processor
Cycle
Cycle
Processor Processor
Cycle
Cycle
Fetch
Decode
Fetch
Execute
Instruction Instruction Operand Instruction
Store
Process
Result Interrupt
DMA
Breakpoints
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Interrupt
Breakpoint
34
DMA / Interrupt Breakpoints
Time
Instruction Cycle
Processor
Cycle
Processor
Cycle
Processor Processor
Cycle
Cycle
Processor Processor
Cycle
Cycle
Fetch
Decode
Fetch
Execute
Instruction Instruction Operand Instruction
Store
Process
Result Interrupt
DMA
Breakpoints
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Interrupt
Breakpoint
35
Precise and Imprecise Interrupts
Properties of a precise interrupt
1. PC (Program Counter) is saved in a known
place.
2. All instructions before the one pointed to
by the PC have fully executed.
3. No instruction beyond the one pointed to
by the PC has been executed.
4. Execution state of the instruction pointed
to by the PC is known.
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Factors affecting Interrupt state
• Pipeline CPU architecture
• Superscalar CPU architecture
• May leave some instructions partially executed
• Does not guarantee “first-come first-served”
• May require extensive state capture
• May require complex logic to capture precise state
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Precise and Imprecise Interrupts (2)
Figure 5-6. (a) A precise interrupt. (b) An imprecise interrupt.
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I/O Efficiency Improvement
• Reduce # of context switches
• Reduce # of data copies in memory as data
passes from device to application
• Reduce # of interrupts
– larger data transfers
– smart controllers
– polling (?)
• Use DMA (increase processing concurrency)
• Balance performance of CPU, memory, bus,
I/O
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User-Space I/O Software
Figure 5-17. Layers of the I/O system and the
main functions of each layer.
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Secondary Storage
•
•
•
•
Basic structure
SSDs
Scheduling Algorithms
Reliability
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Disk Structure
• Addressed as a large, 1 dimensional array
of logical blocks (clusters).
• Blocks are mapped onto disk sectors
– Mapping starts with track 0, head 0, sector 0.
– Continues through sectors on the same track
and head
– Moves to all heads on the same cylinder
– Moves to all cylinders in the drive
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Disk Mechanism
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Magnetic Disks (1)
Figure 5-18. Disk parameters for the original IBM PC 360-KB floppy disk
and a Western Digital WD 18300 hard disk.
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Magnetic Disks (2)
Figure 5-19. (a) Physical geometry of a disk with two zones.
(b) A possible virtual geometry for this disk.
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CD-ROMs
Figure 5-21.
Recording
structure of a
compact disc
or CD-ROM.
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CD-ROMs (2)
Figure 5-22. Logical data layout on a CD-ROM.
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CD-Recordables
Figure 5-23. Cross section of a CD-R disk and laser. A silver
CD-ROM has similar structure, except without dye layer and with pitted
aluminum layer instead of gold layer.
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DVD (1)
DVD Improvements on CDs
1. Smaller pits
(0.4 microns versus 0.8 microns for CDs).
2. A tighter spiral
(0.74 microns between tracks versus 1.6
microns for CDs).
3. A red laser
(at 0.65 microns versus 0.78 microns for CDs).
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DVD (2)
DVD Formats
1.
2.
3.
4.
Single-sided, single-layer (4.7 GB).
Single-sided, dual-layer (8.5 GB).
Double-sided, single-layer (9.4 GB).
Double-sided, dual-layer (17 GB).
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DVD (3)
Figure 5-24. A double-sided, dual-layer DVD disk.
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Solid State Devices
History
• ROM – Read Only Memory - ?
• PROM – Programmable Read Only Memory 1956
• EPROM – Eraseable Programmable ROM - 1972
• EEPROM – Electrically Eraseable PROM – 1978
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Early SSD Issues
• Relatively Low Capacity
• Very Slow ”Erase” times
• High cost per bit.
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Flash Memory
• Developed ~1980
• Memory cells organized into Blocks
– Erase at block level
• Based on Floating-gate Transistors
– Stores a charge between insulating layers
– Can retain a charge “for many years”
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Floating-Gate Transistor
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Floating-Gate Transistor
• Multiple voltages needed to read / write /
erase
– Typically generated with circuitry on device
– Device typically requires standard PC voltages.
• Two types available
– Single Level Cell (SLC) only detects presence or
absence of current
– Multi-level Cell (MLC) detects current level,
allowing storage of multiple bits per cell
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SSD Organization
• Objective is to provide a structure that will
improve performance (write / erase)
• Stored in pages / blocks / planes
–
–
–
–
Typical page sizes: 512 / 2048 / 4096 bytes
Typical block sizes: 32 / 64 / 128 pages
Typical plane sizes: 1024 / 2048 / ???
4096 * 128 * 2048 = 1 GB
• Memory chips may have multiple dies.
• Devices may have multiple chips.
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SSD Performance
Speed
SLC
MLC
Read
25 μs
50 μs
Erase
2 ms per block
2 ms per block
Write
250 μs
900 μs
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SSD Performance
Endurance
• Bit level reliability
– SLC - ~100,000 program / erase cycles
– MLC - ~5,000 to 10,000 program / erase cycles
• Robust ECC
– Correct single bit errors
• Over-provision
– Mark bad memory and move data to good blocks
• Wear leveling
– Write data evenly across storage space
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SSD Products
• Current –
– OCZ Technology
• PCIe – Z-drives 256GB ($1300), 512 GB, 1TB
• 2.5” / 3.5” SATA – 250GB, 500GB, 1TB ($3900)
– Western Digital
• 2.5” SATA – 256GB ($800)
– Corsair , Kingston, Patriot, etc.
• Future
–?
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Hard Disk Formatting (1)
Figure 5-25. A disk sector.
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Disk Format
Figure 5-26. An
illustration of
cylinder
skew.
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Disk Formatting (3)
Figure 5-27. (a) No interleaving. (b) Single interleaving.
(c) Double interleaving.
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Disk Scheduling
• To read or write, the disk head must be
positioned at the desired track and at the
beginning of the desired sector
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Disk Scheduling
• To read or write, the disk head must be
positioned at the desired track and at the
beginning of the desired sector
• Seek time
– time it takes to position the head at the desired
track
• Rotational delay or rotational latency
– time its takes until desired sector is rotated to line
up with the head
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Disk Scheduling
• Access time
– sum of seek time and rotational delay
– the time it takes to get in position to read or write
• Data transfer occurs as the sector moves
under the head
• Data transfer for an entire file is faster when
the file is stored in the same cylinder and in
adjacent sectors
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Disk Scheduling
• Seek time is a reason for differences in
performance (try to minimize)
• For a single disk there will be a number of
I/O requests
• If requests are selected randomly, we will
get the worst possible performance
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Disk Scheduling - Objective
• Objective is to maximize disk bandwidth
– minimize “wasted” time
– seek time dominates
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Disk Scheduling - Objective
• Objective is to maximize disk bandwidth
– minimize “wasted” time
– seek time dominates
• Common example:
– disk head starts on track 53 (range 0 - 199)
– list of pending requests
98, 183, 37, 122, 14, 124, 65, 67
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Disk Scheduling - FCFS
• First-come, first-served (FCFS)
– Process request sequentially
– Fair to all processes
– Approaches random scheduling in performance if
there are many processes
– Avoids starvation
• Example head movement: 640 cylinders
track

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53 - 98 - 183 - 37 - 122 - 14 - 124 - 65 - 67
45 + 85 + 146 + 85 + 108 + 110 + 59 + 2 = 640
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Disk Scheduling - SSTF
• Shortest Service Time First
– select the disk I/O request that requires the
least movement of the disk arm from its
current position
– always choose the minimum Seek time
• Example head movement: 236 cylinders
– 53 - 65 - 67 - 37 - 14 - 98 - 122 - 124 - 183
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Disk Arm Scheduling Algorithms (2)
Figure 5-28. Shortest Seek First (SSF) disk scheduling algorithm.
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Disk Scheduling - SCAN
• SCAN
– arm moves in one direction only, satisfying all
outstanding requests until it reaches the last
track in that direction
– direction is reversed
– (also known as elevator algorithm)
• Example head movement: 236 cylinders
– 53 - 37 - 14 - 0 - 65 - 67 - 98 - 122 - 124 - 183
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Disk Arm Scheduling Algorithms (3)
Figure 5-29. The elevator algorithm for scheduling disk requests.
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Disk Scheduling - C-SCAN
• C-SCAN
– Provides a more uniform wait time than SCAN
– Restricts scanning to one direction only
– When the last track has been visited in one direction,
the arm is returned to the opposite end of the disk
and the scan begins again
– Treats the cylinders as a circular list that wraps
around from the last cylinder to the first one.
• Example head movement: 383 cylinders
53 - 65 - 67 - 98 - 122 - 124 - 183 - 199 - 0 - 14 - 37
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Disk Scheduling - C-LOOK
• C-LOOK
– version of C-SCAN
– Difference is that head arm only goes as far as the
last request in each direction. It doesn’t go to the
beginning or end of the disk automatically.
• Example head movement: 322 cylinders
53 - 65 - 67 - 98 - 122 - 124 - 183 - 14 - 37
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Disk Scheduling - Other Algorithms
• Other Algorithms
– Priority
• goal is not to optimize disk use but to meet other
objectives
• short batch jobs may have higher priority
• provide good interactive response time
– Last-in, first-out
• good for transaction processing systems
– the device is given to the most recent user so there should
be little arm movement
• possibility of starvation since a job may never regain the
head of the line
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Selecting a Disk Schedule
• Performance depends on number and type
of requests
• SSTF is common
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Selecting a Disk Schedule
• Performance depends on number and type
of requests
• SSTF is common
• SCAN, C-SCAN perform better under heavy
load
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Selecting a Disk Schedule
• Performance depends on number and type
of requests
• SSTF is common
• SCAN, C-SCAN perform better under heavy
load
• Modular system design facilitates
replacement
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Error Handling
Figure 5-30. (a) A disk track with a bad sector.
(b) Substituting a spare for the bad sector.
(c) Shifting all the sectors to bypass the bad one.
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Disk Reliability
• Protection for data provided through
cooperative operation of multiple disks
• Multiple copies on multiple disks
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Disk Reliability
• Protection for data provided through
cooperative operation of multiple disks
• Multiple copies on multiple disks
• Multiple interface cards
• Copies on multiple systems
• Tape backups
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RAID
• Redundant Array of Independent Disks
• Designed to provide improved performance
/ data reliability within a single system
using multiple disks
• Multiple versions available (0 - 6)
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RAID 0
• Intended to support improved data transfer performance
through “striping”
• No data redundancy provided…
• I/O performance vs. data transfer performance
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strip 0
strip 1
strip 2
strip 3
strip 4
strip 5
strip 6
strip 7
strip 8
strip 9
strip 10
strip 11
strip 12
strip 13
strip 14
strip 15
85
RAID 1
• Intended to provide a simple mechanism to improve data
reliability using “mirroring”
• Uses 2 (sets of) disks to make identical copies of the
data. Writes must be done to both sets, but reads can be
done by either (synchronize disks)
strip 0
strip 1
strip 2
strip 3
strip 0
strip 1
strip 2
strip 3
strip 4
strip 5
strip 6
strip 7
strip 4
strip 5
strip 6
strip 7
strip 8
strip 9
strip 10
strip 11
strip 8
strip 9
strip 10
strip 11
strip 12
strip 13
strip 14
strip 15
strip 12
strip 13
strip 14
strip 15
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RAID 2
• Data redundancy provided using Hamming code
• Disks accessed in parallel
– Excellent performance for Data transfer, poor for I/O
• Error correction possible
b0
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b1
b2
b2
f0(b)
f1(b)
f2(b)
87
RAID 3
• Data redundancy provided using Bit-interleaved Parity
• Disks accessed in parallel (disks synchronized)
– Excellent performance for Data transfer, poor for I/O
• Error correction still possible
b0
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b1
b2
b2
P(b)
88
RAID 4
• Data redundancy provided using Block-level Parity
• Disks accessed independently
– Excellent performance for I/O, fair for data transfer
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block 0
block 1
block 2
block 3
P(0-3)
block 4
block 5
block 6
block 7
P(4-7)
block 8
block 9
block 10
block 11
block 12
block 13
block 14
block 15
P(8-11)
P(12-15)
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RAID 5
• Data redundancy provided using Block-level Parity
(distributed across disks)
• Disks accessed independently
– Excellent performance for I/O, fair for data transfer
block 0
block 1
block 2
block 3
P(0-3)
block 4
block 5
block 6
P(4-7)
block 7
block 8
block 12
block 9
P(8-11)
block 10
block 11
P(12-15)
block 13
block 14
block 15
block 16
block 17
block 18
block 19
P(16-19)
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RAID 6
• P + Q Redundancy
– Uses error correcting codes (e.g. Reed-Solomon)
instead of parity. Requires multiple redundant blocks
for each “stripe” of data
– Can support multiple disk failures.
block 0
block 1
block 2
block 3
P2
P2
P2
block 5
block 6
P1
block 7
block 4
block 8
block 12
block 9
P1
block 10
P2
block 11
P1
block 13
P2
block 15
block 14
block 16
block 17
block 18
block 19
P2
P1
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RAID 0+1, 1+0
• RAID 0 + 1
– Stripe Disks (RAID 0), then mirror disk set (RAID 1)
– Better performance than RAID 5, but doubles the
number of disks needed
– If 1 disk fails, that mirror is unavailable
• RAID 1 + 0
– Mirror Disks (RAID 1), then stripe the pairs (RAID 0)
– Similar performance to RAID 0 + 1
– Better reliability. If 1 disk fails, remaining pairs are all
still active.
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Summary
• Input / Output Hardware
– DMA, Interrupts, CPU design
• I/O Software
– I/O techniques, device drivers, buffering
• Disks
– Basic structure, Scheduling Algorithms, Reliability
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References
• Anatomy of SSDs – www.linuxmag.com/id/7590/1/
• Storage networking Industry Association – SNIA
– Solid State Storage Initiative (SSSI)
www.snia.org/forums/sssi
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Questions
• How does DMA improve the performance of common disk
operations (reading and writing)?
• In terms of I/O operations, what is the difference between
temporary and permanent failures? Provide an example of
each.
• On hard disks, the length of the inner track is perhaps 2/3 of
the outer track. How do modern disks deal with the
difference in the amount of space available to write data?
• On optical storage (CDROM, DVD, etc.) how have
manufacturers been able to increase the capacity of the
disks?
• In disk scheduling, what is the difference between the SCAN
algorithm and C_SCAN?
• Which RAID configuration (s) provide a complete duplicate of
all of the data?
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