Transcript Architecher (1)

Computer Architecture
&
Design
Sentan Jouhou
Prof. M.R.Asharif
University of the Ryukyus
Department of Information
Engineering
Introduction to
Computing System


History and Difinition
Definition: Acomputer is a device
capable of solving problems or
manipulating information,
according to a prescribed
sequence of instructions
(program), using some mechanical
or electrical ( or else) process.
Human began to solve problems
since several thousand years ago


Computers can handle more
complicated problems :
Communications, Control, Robots,
games, Manufacturing
Computer Revolution
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Abacus: is used over 3000 years
Slide Ruler: by J. Napier in 1600
Mechanical Computer: by B.
Pascal in 1642
In 1820, C. Babbage built
Polynominals evauation machine
In 1930, H. Aiken and G. Slibitz
developed calculator by relays
In 1940, ENIAC was built by J.
Mauchly and J. Eckert
Three most important
discoveries:

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Proposing program reside in computer
memory, by J. Von Neumann
Transistor invention in 1947 by J. Bardeen,
W. H. Brattain and W. Schockley
Magnetic core memory developed at MIT
by J.W. Forrester
Generations of Computer
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1st-generation: ENIAC, 1940~1950
2nd-generation: Transistor computers 1950’s
3rd-generation: Integerated Circuit (IC)
1960~1970’s
4th-generation: LSI and VLSI, PC, Workstations
5th-generation: Not only hardware but software:
Voice Activation, Parallel Processing, Neural
Networks, AI, Optical Processing, Visual
Programming, Gigabit Networks,
Hardware Components &
Computer Construction
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IC: Contains several gates
SSI: Contains 1 to 10 gates
MSI: Contains 10 to 100 gates
LSI: Contains 100 to 10,000 gates
VLSI Contains more than 100,000 gates
Important Electronic
Technologies
Technology
Device Type Power Consumption Speed

RTL Bipolar Junction High
DTL
//
//
//
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TTL
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//
//
ECL //
//
p-MOS MOSFET
n-MOS
//
c-MOS
//
GaAs
//
Medium
Low
//
Medium
Packaging
Discrete
// SSI
SSI, MSI
High
High
SSI, MSI, LSI
Medium
Low
MSI, LSI
Medium Medium
MSI,LSI,VLSI
Low
Medium SSI,MSI,LSI,VLSI
High
High
SSI,MSI,LSI
Technology Changes
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vacuum tube  transistor  IC  VLSI
Moore’s law: number of transistors on a
single chip doubles every 1.5 years
Consequences of Moore’s law (and other
improvements):
 processor
performance and memory capacity
double every 1.5 years
 computers get smaller, faster and cheaper
Moore’s law
What Computers Are
Computer?



Computers are programmable electronic
devices.
They solve problems using algorithms.
They consist of hierarchical layers of
hardware and software.
What is Computer?
Computer is a
machine for
processing, storing,
and retrieving data.
1) processor, memory, devices and so on.
2) firmware, bootloader, operating system, application
Computer is
composed of
hardware1) and
software2)
An Algorithm

Compute the average age of a group of
people.
 1.
n = number of people
;input
 2. sum = 0
 3. i = 1
 4. sum = sum + age of person i ;input
 5. i = i+1
 6. if i  n then go to 4
 7. sum = sum/n
 8. average age = sum
;output
What Algorithms Involve
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data (inputs & outputs)
operations
control (order of operations)
Different Hardware Layers
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structures on silicon or other materials
electronic components (transistors etc.)
logic components (gates, flip-flops)
logic circuits (adders, registers, counters, etc.)
functional units (ALU, multiplier, shifter,
register file, control unit)
computer components (CPU, memory, I/O
unit)
computer system
Software Layers

Machine language
 0010
1011 1101 1000
 1001 0111 0101 1110

Assembly language
 MOV A,
#3CH
 ADD A, 20H

High-level language
y
= 15;
 x = (y=y-5, 30/y);
Two Concepts;

Computer architecture


Like: instruction set, data types, I/O
mechanisms, addressing of memory
Computer organisation

like: operational units and their
interconnections, peripheral interfaces,
memory technology
An Example
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Architectural issue: has the computer a
multiply instruction or not?
Organisational issue: has the computer a
special multiply unit or does it repeatedly use
the add unit?
Organization of a Digital Computer
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ALU: Arithmetic Logic Units
Control Units
Memory or Storage Units
I/O equipment (peripheral devices
I/O
ALU
Control
Memory
Block Diagram
Central
Processing
Unit
Main
Memory
Input/
Output
System Interconnection
Block Diagram (continued)
CPU
Control
Unit
Arithmetic
& Logic
Unit
Registers
Internal CPU Interconnection
Block Diagram (continued)
Control Unit
Sequencing
Logic
Registers
& Decoders
Control
Memory
Computer Blocks
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CPU (Central Processing Unit)
ALU (Arithmetic and Logic Unit): calculations
Register unit: data, memory addresses
Control unit: control of the whole computer
Memory: data, programs
I/O unit: communication with the surroundings
Central Processing Unit

Control Unit
 Coordinates

the operation of the computer.
Arithmetic and Logic Unit
 Performs
arithmetic operations.
 Performs logical operations (AND, OR,
SHIFT).

Registers
Other Components

Memory
 Stores

instructions and data.
Input/Output
 Called
peripherals.
 Used to input and output instructions and data.

System Interconnection
 Bus.
Control Unit


Generates control signals –
Connect registers to the bus.
Control the function of the ALU.
Provide timing signals to the system.
All actions of the control unit are
associated with the decoding and
execution of instructions (fetch and
execute cycles).
Memory

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Each memory location has a unique
address.
To write the data on present address.
To read the data from present address.
The Memory Hierarchy
Functional Behavior of a RAM Cell
Simplified RAM Chip Pinout
A Four-bits
Memory with
Four Bits per
Word in a 2D
Organization
2-1/2D Organization of a 64-bits by
One-Bit RAM
Bus
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Communicate between parts of the computer.
Only one transmitter and one receiver at a
time.
2 levels — Internal, External
Groups of signal lines — address, data,
control.
Example
Bus
Basic System
Architecture
Control unit fetches an
instruction from memory for
execution for following
operations
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Arithmetic instruction such as: +, X, -, /
Test and compare operations >, <, =, ...
Branch or skip instructions
I/O Commands
Logic and shift operations
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Numerical data are stored in binary number
system and 2’s complement system
Non-numeric I/O codes (alphanumeric symboles)
are allowed which is called the character set,
binary-like code called: The American Standard
Code for Information Interchange (ASCII)
Example: ADD 1
Symbol
ASCII CODE
---------------------------------A
01000001
D
01000100
D
01000100
00100000
1
00110001
Number System and Codes
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Digital systems can process binary digits 0’s and
1’s
Positional number system (radix 10 for traditional
number system
1734.6=1*1000+7*100+3*10+4*1+6*0.1
Binary number: radix 2 for digital system
101.001=1*4+0*2+1*1+0＊0.5+0*0.25+1*0.125
=5.125
Octal number: radix 8
100011001110=100 011 001 110=(4316)8
Hexadecimal number: radix 16
101110101001=1011 1010 1001=(BA9)16
Converting from Octal and
Hexadecimal to binary:
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(1357.17)8 =001 011 101 111.001 111
(9F.4C)16=1001 1111.0100 1100
Converting from Octal and
Hexadecimal to decimal:
(436.5)8=4*64+3*8+6*1+5*0.125=286.625
(F1A3)16=15*16*16*16+1*16*16+10*16+3*1=61859
2’s Complement System
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2’s complement system easily handle
mathematics operation
[N]2=2^n-(N)2 , n= number of digits
Ex: (N)2=01100101 , n=8
[N]2=2^8-01100101
=100000000-01100101=10011011
Rule: complement all bits, then add 1
01100101 10011010+1=10011011
11010100
00101011+1=00101100
Computer Arithmetic
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In digital computers all number
converted to 2’s complement and
perform the required arithmetic
Machines with n bits can represent
integers in the range: -2^(n-1)=<
N=<2^(n-1)-1
1000…0=<N=<0111…1
Outside this range results in an
overflow which should be informed
Computer Codes
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1-Numeric Codes:
Fixed-Point
Floating-Point
Mantissa sign (SM)
Sign bit .
Magnitude
Exponent (E)
-
Mantissa (M)
N=M*2^E

M=SM.an-1…a-m
E=be-1be-2…bo
Computer Codes (continue)
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2-Character Codes: To represent
characters in computer:
Binary Coded Decimal (BCD)
ASCII codes
Gray Codes
3-Error Detection and Correction Codes
From Analog to Digital
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Analog Circuit: Voltage can change
continuously
Digital Circuit: Allowed only for two level “0”,
“1”
Switches have two states (ON, OFF)
Diodes have two states (Conducting current,
Not conducting)
Transistors in switching mode have two
states (High collector current, Low collector
current)
Logic Gates
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AND Gate: A.B
A (0/1)
B(0/1)
C
A
0
0
1
1
B
0
1
0
1
C
0
0
0
1
Logic Gates
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OR Gate: C=A+B
A (0/1)
B(0/1)
C
A
0
0
1
1
B
0
1
0
1
C
0
1
1
1
Logic Gates
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NOT Gate: C= A
A (0/1)
C (1/0)
A
0
1
C
1
0
Logic Gates
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NAND Gate: A.B=A+B
A (0/1)
C
B(0/1)
A
0
0
1
1
B
0
1
0
1
A.B
1
1
1
0
Logic Gates
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NOR Gate: A+B=A . B
A (0/1)
C
B(0/1)
A
0
0
1
1
B
0
1
0
1
C
1
0
0
0
Logic Gates
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EX-ORAND Gate: C=A B=A . B+B . A
A (0/1)
C
A
B
B(0/1)
0
0
0
1
1
0
1
1
C
0
1
1
0
Boolean Algebra & Venn diagram
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In digital computer circuits, to investigate about logic
functions we use Boolean algebra (G. Boole 181564) which uses two values (0,1 or True, False or
High, Low) for switching logic functions.
Venn diagram is geometrical representation of
functions in Boolean algebra (set theory) by
assigning a circle to a variable
A+ A= 1
A
A
Intersection= A . B
Union= A + B
Let’s show the following
functions:
A.B
A+B
De Morgan Theorem:
A. B =A+ B
A. B=A+ B
A
A.B
A+ B =A. B +A. B +A. B
A.B
By Venn diagram, we can
proof the Boolean algebra
relations:
A . B+ A. B = A
B
Karnaugh Map
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
We can draw the Venn diagram for more
than two variables ( for 3).
But for more than 3 variables its shape
should be changed to rectangular, which
is called Karnaugh Map.
wx
y
w
00
yz
00 0
01
4
11
12
10
8
01
1
5
13
9
11
10
3
2
7
15
14
11
6
10
z
Logical Postulates
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1 . 1=1
0+0=0
1 . 0=0
0+1=1
0 . 0=0
1+1=1
0 . A=0
0+A=A
1 . A=A 1 + A=1
Commutative Laws: A + B=B + A, A . B=B.A
Associative Laws: A+(B+C)=(A+B)+C
A . (B . C)=(A . B) . C
Distributive Laws: A+BC=(A+B)(A+C)
A(B+C)=AB+AC
Idempotence Laws: A+A=A, A.A=A
Logical Postulates (continue)
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Complementary Laws: A+A=1, A.A=0
Absorption Laws: A+AB=A, A(A+B)=A
A+AB=A+B
Involution
(A)=A
Inversion Laws (De Morgan’s theorem):
(A + B) = A . B
A.B=A+B
Example

F=A+B+C

F=A+B+C=A.B.C
Truth Table- Analysis


Investigating absorption law:
A+A.B=A+B
A
0
0
1
1
B A+B A AB
0
0
1
0
1
1
1
1
0
1
0
0
1
1
0
0
A+A.B
0
1
1
1
Synthesis

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From input-output values, we want
to built the logic function
From OR of AND inputs for which
the output is “1”
From AND of OR inputs for which
the output is “0”(with complement)
Design of Sign of multiplier


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Truth table for sign of multiplier
A
B
AXB
-1 -1
+1
-1 +1
-1
+1 -1
-1
+1 +1
+1
Synthesis (continue)
Converting:
0
-1
1
+1

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A
B
f(A,B)
0
0
1
0
1
0
1
0
0
1
1
1
To find the function f(A,B):
f(A,B)=A . B + A . B
Synthesis (continue)

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
Using De Morgan’s theorem:
f(A,B)=A . B+A . B=(A+B)(A+B)
=A.A+A.B+B.A+B.B=A.B+B.A=
=A B
Therefore: f(A,B)=A B
Equivalently, we could obtain this
result from OR of AND’s where the
output is zero (complementary):
f(A,B) = A . B + A . B
Design of a Sign Multiplier
AB
A
A
f=AB+BA
B
B
BA
Principle of Digital Circuits

Diode-Resitor Logic Cicuits (DRL):
+V
A B
-V -V
-V +V
+V -V
+V +V
F
-V
-V
-V
+V
F=A.B
A
B
If +V=1, -V=0 Then AND
If +V=0, -V=1 Then OR
A
0
0
1
1
B
0
1
0
1
F
0
0
0
1
Principle of Digital Circuits

Diode-Transistor Logic Cicuits (DTL):
+V
F=A.B
A B
-V -V
-V +V
+V -V
+V +V
F
V
V
V
-V
A
B
If +V=1, -V=0 Then NAND
-V
A
0
0
1
1
B
0
1
0
1
F
1
1
1
0
Principle of Digital Circuits



Direct-Coupled Transistor Logic (DCTL):
Transistors as switch can be coupled
directly to each other to form NAND or
NOR gates.
Coupled in series: NAND
Coupled in parallel: NOR
Principle of Digital Circuits




Current Mode Logic (CML):
With a constant current that
switches from one transistor to
another is CML
Merit of CML: very high speed
(1nsec or less)
Demerit of CML: High power
consumption


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
Transistor-Transistor Logic (TTL):
If at an input of NAND gate we use multi-transistors
and another for inversion, we a TTL NAND gate.
TTL Families:
7400: Package four 2-input TTL NAND gates
74 H: High speed TTL 33% reduction in Propagation
delay
74 L: Low power TTL (90% reduction)
Schottky Transistors: avoid saturation by using
schottky diod. 74 S family: high speed low power.
74 LS family faster than 74 and 1/5 power. 74 AS
twice faster than 74 S same power. 74 F (Fairchild)
same as 74 AS. 74 ALS rival to 74 LS.
Metal-Oxide Semiconductors (MOS)


TTL and CML & ECL have high
power consumption, so they have
limitation in number of gate in a
single chip fabrication. If too many
gates are put together, they will
burn out.
MOS transistors in contrary have
less power consumption, so they
are very interesting for high
integrated circuit of today.
Metal-Oxide Semiconductors (MOS)






A MOS is a 3 terminal device that
acts like a voltage controlled
Drain
resistor.
Gate
+
ON: Low resistor
Source
Vgs OFF High resistor
In n-MOS (n-channel MOS)
Vgs=0:
Rds=high: M-OHM
Vgs:Positive: Rds=low: 10 OHM
Metal-Oxide Semiconductors (MOS)





In p-MOS (p-channel MOS):
Vgs=0:
Rds=high
Vgs=negative: Rds=low
Input impedance of MOS gate is very
high
MOS are also called Field Effect
Transistor (FET or MOS-FET)
Metal-Oxide Semiconductors (MOS)



Compementary MOS (CMOS) Logic:
To reduce power consumption and
increase speed, CMOS is formed by
totem pole structure with an n-MOS and
a p-MOS
Out
In either state one
In

transistor is in OFF state
Sequential Logic Circuits



In combinational circuits, output is
dependent on the current input
(memory-less circuits).
In sequential circuits, output is
dependent on order of the input
came before.
There is usually a feedback loop in
sequential circuits.
Flip-Flops as a memory unit-bit
Flip-flops are sequential circuits
and they work as a logic memory
unit with stable two states.
The RS flip-flop:


S=1
Q=1
R=0
Q=0
S=0
Q=0
R=1
Q=1
S=0
Rest Condition
R=0
No change
S=1 Not permitted Q=0
R=1
Q=0
{
{
{
{
S
R
Q
Q
10
00,01
0
01
State-Diagram
00,10
1
Logic Circuit for RS Flip-Flop
S
RS flip-flops are available in package
of four RS-FFs in one IC such as:
74 LS 373 or 74 LS 374
With DTL: response time: 30-50 nsec R
and power dissipation: 20 mW
With TTL: response time: 10-20 nsec
With ECL: response time 5 nsec or less
Q
Q
D-Latch Flip-Flops
C
1
1
0
D
0
1
X
D
C
Q
Q
0
1
1
0
Q(n-1)
D
C
Q
Q
Q
Q
Edge-Triggered D Flip-Flop
D
QM
D
C
Q
D
C
Master FF
CLK
Q
Q
Q
Q
Slave FF
The output is only changed in rising edge of Clock
D
0
1
X
X
CLK
0
1
Q
0
1
Q(n-1)
Q(n-1)
Q
1
0
last
last
D
CLK
Q
Q
JK Flip-Flop
J
CLK
K
J
0
0
1
1
K
0
1
0
1
Q(n+1)
Q(n)
0
1
Q(n)
S
Q
R
Q
Q
Q
T Flip-Flop
T
0
1
T
Q(n+1)
Q(n)
Q(n)
D
CLK
Q
Q
Using D-FF
T
1
T
Q
Q
J
CLK
K
Q
Q
Using a JK-FF
Shift Registers
SERIN
D
CLK
Q
D
Q
D Q
…….. D
Q
SEROUT
Counter
1
Input
J
C FF0
K
Q
J
C FF1
K
Q
J
C FF2
K
Q
Reset
Cascade Flip-Flops as a Counter
J
C FF3
K
Q
A/D-D/A Convertors
0
V
2
1 V
2
2 V
2
V
3
2
8R
4R
2R
Op-Amp
R
Digital to Analog Convertor
Analog to Digital Converter
Digital Output
…….
CLK
Binary Counter
Start Pulse
Analog Input
S
R
FF
Q
Q
Voltage Comparator
Linear Ramp Generator