Transcript Sami_Vaehanen_

3D INTEGRATED APPLICATIONS FOR HEP
MUX 2010 WORKSHOP
SAMI VÄHÄNEN – CERN PH-ESE
1
Outline
•Introduction
•Large-area tiling
•Assembly processes
•Considerations about sensor wafers
•Through Silicon Via (TSV)
•Examples of TSV development work within HEP community
•Summary
2
Introduction
•This presentation focuses on 3D integrated pixel detector structures using
advanced manufacturing and packaging processes.
•We assume that process scaling will permit the integration of the readout
electronics in a single CMOS layer.
•Aspects related to tiling of detectors will be presented.
•TSVs and edgeless sensors chips are needed
•Guidelines will be given for economical detector designs.
•The best possible performance and low cost requirements do not meet
•Wafer-level assembly processes are foreseen in future.
•Typical Through Silicon Via (TSV) scenarios are described, and some of the
prototyping work done within HEP community is briefly described.
3
Pixel Detectors
•Pixel detector consists of a sensor and a readout chip with pixel matrix, which are
connected with flip chip interconnects.
•Because each pixel is visible in the radiation image, a high bump bonding yield is
required to avoid visible defects.
•Solder bumps have been typically used as connecting the chips electrically and
mechanically together.
4
Future Pixel Detector Structures
•Via last process using existing/new readout chip designs (picture on the left)
•Status: prototyping phase
•Via middle process with very advanced designs (picture on the right)
•Status: R&D phase ongoing by some HEP groups
Edgeless
sensor chip
Edgeless sensor
chip
sv
Solder µbumps
µ-bump
interconnections
ROC analog
module
TSV
TSV’s
Readout chip
Redistribution
layer
TSV’s
BGA bumps
Solderable
BGA UBM
Thin
interconnections
(Cu-Cu)
ROC digital
module
Redistribution
layer
TSV
Light weight
joints
BGA
bumps
Low-mass carrier
board
Illustration of via-last
structure
Low-mass carrier
board
Illustration of viamiddle structure
5
Process Flow for Complete 3D Integration
1. Probing of wafers to select Known Good Die (KGD)
2. Thinning of wafers
3. Through-Silicon-Vias (TSV) for readout chips
•
•
•
Etching, insulation, deposition of barrier and seed layers
Via last and via middle process alternatives
Good TSV process yields required (no testing possibility before flip chip assembly)
4. Redistribution layer and solderable UBMs
•
Thin UBMs could be processed on pixels already prior to the TSV process (via last)
5. µ-bumping of active side of the readout wafer
6. Edgeless sensors chips – sensors are manufactured parallel to the TSV process.
•
Sensor designs with guard rings do not make sense (explanation later).
7. µ-bumping or UBM deposition for bump pads
8. Flip chip assembly
•
•
Chip-to-Chip (C2C) and Chip-to-Wafer (C2W) bonding
Wafer-to-Wafer (W2W) bonding is a distant dream
9. De-bonding of wafers
10. Electrical testing (this late!)
•
From BGA pads
11. Mounting of detectors on carrier boards
•
Brainstorming needed for low mass joints
6
LARGE AREA TILING
7
Large Area Tiling
•TSVs and edgeless sensors needed – seamless tiling
•Although TSVs will be expensive, detectors panels can be made in cost-effective way.
•Tiling single detectors (single ROCs on single sensor assemblies) into an array
•Good process yields required (example below)
•No testing possibility of ROCs in between TSV process and flip chip assembly.
•Assumption that FC assembly won’t be expensive
•Let’s imagine a case where 4x4 array of ROCs (with TSV’s) is FC assembled on a single
sensor:
•TSV process has a yield of 95 %, RDL yield 98 %, flip chip assembly 97%, and sensor yield 90%
(very good yields).
•Yield of a single chip assembly is about 82 %
•Solder bumping yield has been ignored
8
Large Area Tiling
•To build detector panels the packaging processes can’t be expensive.
•One should not go to the extremes but stick to what is good enough
•The optimization of tiling should be thought well before design of chips.
•It is evident that one ROC (with TSVs) on single sensor is a cost-efficient solution (shown
on previous slide).
•Very light weight substrate (carrier board) and availability with good yields needed.
•Rigid/Flex?
•Diamond?
SENSOR
SENSOR
SENSOR
READ OUT CHIP
READ OUT CHIP
READ OUT CHIP
SENSOR
READ OUT CHIP
CARRIER BOARD
READ OUT CHIP
READ OUT CHIP
CARRIER BOARD
Good solution
Bad solution
3D integrated
assembly from side
Tiling of assemblies from top. Left: Single dies used, Right: large sensor used
9
Detector Packaging vs. Fill Factor
•A simple calculation vs. graphic example is given:
•“Read out at the end of column” structure with wire bonding pas
•Ordinary sensors with guard ring and edgeless sensors compared
•High density (very advanced) TSV scenario - taking the I/O’s through the ROC in proximity of
the pixels.
Structure
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
17 mm
17 mm
Conventional
Sensor chip
17 mm
Readout chip
15 mm
Guard ring
1 mm
15 mm
Readout Chip (ROC)
10
Conventional Approach
Parameters used in calculations:
Periphery with wire bond pads
Periphery without wire bond pads
Space reserved for wire bonds
Tiling - gap between assemblies
Structure
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
(mm)
2
0.8
1
0.2
SENSOR
READ OUT CHIP
CARRIER BOARD
Cross-section
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
17 mm
Periphery
Sensor chip
17 mm
Guard ring
1 mm
11
2 mm
0.8 mm
Conventional Approach
Parameters used in calculations:
Periphery with wire bond pads
Periphery without wire bond pads
Space reserved for wire bonds
Tiling - gap between assemblies
Structure
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
(mm)
2
0.8
1
0.2
SENSOR
READ OUT CHIP
CARRIER BOARD
Cross-section
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
After FC assembly
Fill factor:
Unit:
73.5%
Array:
69.5%
12
Conventional + Edgeless Structure
Parameters used in calculations:
Periphery with wire bond pads
Periphery without wire bond pads
Space reserved for wire bonds
Tiling - gap between assemblies
Structure
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
(mm)
2
0.8
1
0.2
SENSOR
READ OUT CHIP
CARRIER BOARD
Cross-section
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
Edgeless Sensor
15 mm
2 mm
0.8 mm
15 mm
Periphery
13
Conventional + Edgeless Structure
Parameters used in calculations:
Periphery with wire bond pads
Periphery without wire bond pads
Space reserved for wire bonds
Tiling - gap between assemblies
Structure
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
(mm)
2
0.8
1
0.2
SENSOR
READ OUT CHIP
CARRIER BOARD
Cross-section
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
After FC assembly
Fill factor:
Unit:
88.8%
Array:
83.2%
14
Peripheral TSVs + Conventional Sensor
Parameters used in calculations:
Periphery with wire bond pads
Periphery without wire bond pads
Space reserved for wire bonds
Tiling - gap between assemblies
Structure
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
(mm)
2
0.8
1
0.2
SENSOR
READ OUT CHIP
Cross-section
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
TSVs
17 mm
Guard ring
Sensor
17 mm
Readout Chip (ROC)
1 mm
15
Peripheral TSVs + Conventional Sensors
Parameters used in calculations:
Periphery with wire bond pads
Periphery without wire bond pads
Space reserved for wire bonds
Tiling - gap between assemblies
Structure
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
(mm)
2
0.8
1
0.2
SENSOR
READ OUT CHIP
Cross-section
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
Readout Chip (ROC)
After FC assembly
Fill factor:
Unit:
77.9%
Array:
77.7%
16
Peripheral TSVs and Edgeless Sensors
Parameters used in calculations:
Periphery with wire bond pads
Periphery without wire bond pads
Space reserved for wire bonds
Tiling - gap between assemblies
Structure
(mm)
2
0.8
1
0.2
SENSOR
READ OUT CHIP
Cross-section
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
Sensor
15 mm
15 mm
Readout Chip (ROC)
17
Peripheral TSVs and Edgeless Sensors
Parameters used in calculations:
Periphery with wire bond pads
Periphery without wire bond pads
Space reserved for wire bonds
Tiling - gap between assemblies
Structure
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
(mm)
2
0.8
1
0.2
SENSOR
READ OUT CHIP
Cross-section
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
Readout Chip (ROC)
After FC assembly
Fill factor:
Unit:
94.9%
Array:
94.7%
18
High Density TSVs and Edgeless Sensors
Parameters used in calculations:
Periphery with wire bond pads
Periphery without wire bond pads
Space reserved for wire bonds
Tiling - gap between assemblies
Structure
(mm)
2
0.8
1
0.2
SENSOR
READ OUT CHIP
Cross-section
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
15 mm
High density
area array
TSVs – chip
periphery
minimized
15 mm
Sensor
15 mm
15 mm
Readout Chip (ROC)
19
High Density TSVs and Edgeless Sensors
Parameters used in calculations:
Periphery with wire bond pads
Periphery without wire bond pads
Space reserved for wire bonds
Tiling - gap between assemblies
Structure
Conventional detector with wire bonds
• Edgeless sensor
ROC with peripheral TSVs – no WB pads
• Edgeless sensor
ROC with high density TSVs - no periphery
(mm)
2
0.8
1
0.2
SENSOR
READ OUT CHIP
Cross-section
Readout chip
(mm)
Sensor chip
(mm)
Combination
(mm)
Area
Active area
Fill factor
(single chip)
Fill factor 10 x 10
array (%)
17 x 15
17 x 17
18 x 17
306
225
73.5
69.5
17 x 15
15 x 15
17 x 15
255
225
88.2
83.2
15.8 x 15
17 x 17
17 x 17
289
225
77.9
77.7
15.8 x 15
15 x 15
15.8 x 15
237
225
94.9
94.7
15 x 15
15 x 15
15 x 15
225
225
100.0
99.8
Readout Chip (ROC)
After FC assembly
Fill factor:
Unit:
100%
Array:
99.8%
20
ASSEMBLY PROCESSES
21
Flip Chip Bonding
•High-accuracy flip chip bonders are able to perform with ± 1 µm precision.
•Existed already for 10 years and it is seems to be sufficient for majority of applications
•Systems required for better than ± 5 µm accuracy are slow
•High number of I/O’s with fine pitch on large chips set requirements on machines:
•High thermocompression force
•Good placement accuracy
•Chip to substrate leveling capabilities
•Good thermal stability
•Low throughput and small assembly batches
•Very expensive ≈ EUR 100 per FC placement
•New wafer level assembly processes are foreseen to lower the assembly costs.
Throughput/h
Accuracy 3σ
Leveling
Datacon 8800 series
Datacon
FC250
FC150
8500
200
70
± 5 µm
no
± 1.5 µm ± 1.5 µm
Yes
Throughputs are optimistic
estimates
Yes
S.E.T. FC150
22
Chip-to-Wafer (C2W) Bonding
•C2W bonding is done on a flip chip bonder, which has a large chuck (200 - 300 mm).
•C2W bonding is more flexible than Wafer-to-Wafer (W2W) bonding and doesn’t
suffer from yield issues.
•Technology benefits
•C2W reduces manual handling of assemblies.
•Increase in the throughput – the whole wafer has to be assembled at the time.
•Sensors can be assembled on known good dies (KGD) – economically wise and efficient.
•Chips with different sizes can be bonded – flexibility!
•C2W bonding is used in industry, but it is not common for assembly of pixel detectors.
Edgeless sensor chips or ROC’s
with TSV’s needed - large
guard ring structures consume
wafer estate.
23
C2W Bonding (cont’d)
•In C2W assembly, the thermal budget seen by the populated chips is larger than in
chip-to-chip assembly
•Solder structures used in C2W assembly must remain solderable during the long assembly
cycle (potentially hours).
•Solid-Liquid-Inter-Diffusion (SLID) AKA Transient-Liquid-Phase (TLP) soldering preferred –
especially in multilayer assemblies!
•Oxide-to-oxide bonding combined with metallic contacts is also interesting
•Common assembly cycle:
a) Tack-bonding (pick & place) of individual chips + mass reflow for the device wafer in
reducing ambient.
b) Collective bonding can be done in wafer bonder after tack bonding with a cover wafer
(slow processes such as hybrid-metal bonding).
•If fluxes are used they have to be thin and spun on wafers.
•C2W bonding is favored when large and expensive dies are used (pixel chips).
If two side processed chips are used, multilayer chip stacking is possible
C2W Bonding Using Build-Up Wafers
•Readout wafers are diced and the good known dies are selected and pick and placed
on carrier wafer with an adhesive layer.
•A build-up wafer with unique stepping can be made.
•C2W is possible for sensors with guard rings
•After assembly, the wafer is diced, and the glue will be dissolved.
•Carrier chips protect the assemblies
•Technology benefits
•One can populate wafers with KGD to get fully electrically functioning wafers
•There are no restrictions for sensor die size
KGD’s are pick & placed on an adhesive layer
Sensor chips are assembled on ROC’s25
Wafer-to-Wafer (W2W) Bonding
•Although W2W would be the ultimate assembly process, it has major restrictions.
•Electrical yields have to be good > 90 % on wafers.
•Wafer bonding compatible designs are required - same chip size and stepping is required.
•Edgeless sensor wafers needed –CMOS wafer area is too expensive to be wasted
•W2W bonding requires high volumes – application driven technology.
•One of the bonded wafers has to be double-side processed to dice the wafer afterwards.
•Wafer cleanliness has an utmost importance – a single 1 µm particle can ruin the process.
•Typically wafer probing is not possible before bonding.
•Small chips are favored for W2W bonding  better yields.
•Sensor wafers are not available in 8” size – not to speak of edgeless sensor wafers.
YB = 95 %
bonding yield
BAD
BAD
BAD
BAD
BAD
BAD
BAD
BAD DAB
BAD
BAD
YR = 75 % yield
YS = 88 % yield
DAB
YR x YS x YB = 63 % yield
26
Readout wafer is flipped and bonded against readout wafer
CONSIDERATIONS ABOUT SENSOR
WAFERS
27
Readout Wafers Used at CERN
•200 mm IBM CMOS wafers manufactured either with 130 nm or 250 nm CMOS
technology.
•CMOS processes of 65 nm and below will be on 300 mm wafers.
•With customized chip designs (not using standard libraries) the wafers have
relative low electrical yields (50 % – 60 %).
•Readout chips are typically fairly large in size and that affects the yields.
•Electrical yields should be better:
•Better than 90 % before wafer bonding becomes an alternative.
•Commercial high yield TSV’s needed
•About 100 TSV’s needed per assembly
28
Sensor Wafers Used at CERN
•High resistivity silicon (many kΩcm) sensor wafers are commonly available in
several sizes (100, 125 & 150 mm), but not in 200 mm size.
•Typical resistivity of sensors is in the range of 4 – 6 kΩcm.
•Depletion of the whole volume of a thick (~ 300 µm) sensor chip
•Wafers are typically processed in small fabs with modest manufacturing
processes and process equipments.
•Issues in potential wafer bonding scenario
•Sensor wafers have often high stresses which results as wafer bow.
•Typically high stress in the passivation layer.
•In future, thinner wafers are needed to reduce the radiation length.
29
Sensor Wafers in 200 mm Size?
•To fully benefit from 3D integration, high volumes and low manufacturing costs,
sensor and readout wafers should be wafer bonded.
•Heterogeneous wafer-level integration
•Sensor wafers have to be 200 mm in diameter
•Edgeless sensor chips structures needed
•Identical chip sizes and stepping
•Many outstanding issues…
•Wafer bonding allows super thin wafers.
•Carrier wafers needed in processing
•Chip handling is very problematic without wafer bonding
•It is foreseen that sensors could be thinned below 50 µm.
•Very low mass in HEP experiments
•Enhanced radiation hardness
30
Thickness of Sensor Wafers
•Sensor silicon might be available in 200 mm size if sensors are made thin enough.
•Resistivity vs. thickness of depletion layer plot shown below
•Curves drawn with different bias voltages (10 – 100 V) at room temperature
X D  2e  (V0  VB )
XD= Thickness of depletion layer
ε = Relative permittivity (1.054*E-12 Fcm-1)
µe= Electron mobility (1500 cm2s-1)
ρ= Resistivity (Ωcm)
V0= Built-in voltage (0.7 V)
VB= Bias voltage
Simplified formula:
X D  0.56   VB )
Thanks to L. Tlustos
31
Edgeless Detectors
•Previously shown example on the fill factor showed the importance of making
edgeless detectors.
•Combined with TSV’s, a four-side-buttable detector tiles can be manufactured.
•Edgeless sensors have been shown with 100 mm and 150 mm Si wafers.
•It will take some years before edgeless detectors will be available on 200 mm
wafers with good yields.
•High quality process facilities needed – wafer-level assembly processes are
very sensitive to particles
•Thin edgeless chips are known to be fragile
•Advanced carrier wafer technologies needed
32
VTT’s Edgeless Sensors – Poly Process
•Thick polysilicon is used for filling
the trench
•High film stresses.
•Fragile chips
•Stresses may be compensated by
depositing thin films on the wafers.
•Troublesome
Poly process, p-on-n
6 um thick inactive polysilicon
Edgeless strip chip from top
Courtesy of VTT
Cross-sectional cut
[email protected]
VTT’s Edgeless Sensors – Edge Implantation
•Advanced edge implantation
process.
•Straightforward and stress-free
processing without the long
deposition step of polysilicon.
•1 µm inactive region at chip edge.
Edge implantation, p-on-n
Edgeless strip chip from top
Courtesy of VTT
Cross-sectional cut
[email protected]
THROUGH SILICON VIAS (TSV)
35
TSV Materials
•Many TSV categories: via first prior to FEOL (front end of the line), via middle
between FEOL and BEOL (back end of the line) , via last post-BEOL or via after
bonding.
•Via first and via middle.
•Via diameters 1-5 µm with sub 10 µm pitch (AR 1 - 10 : 1)
•Via last & via after bonding: post-processing of TSV’s on a pre-manufactured wafer.
•Via diameters 5 – 100 µm with 10 – 150 µm pitches (AR 1 - 5 : 1)
•In via first TSV processes the thermal restrictions are loose but only polysilicon
can be used. Good electrical conductor materials do not exist in FEOL processes.
•With BEOL or post-BEOL TSV processes, the melting point of aluminum and
thermal stresses sets the process temperature maximum (T < 450 ̊C).
•Via middle metal resistivities: CVD tungsten 8 – 15 µΩcm , Cu 1.7-2 µΩcm.
•Coefficient of thermal expansions: W = 4.5 PPM/˚C, Cu: 16.8 PPM/˚C
36
Via First, Via Middle or Via Last???
C
a
r
r
i
e
r
Comment: polysilicon (must withstand 1000 ˚C FEOL process temperature)
w
a
f
e
r
s
Comment: CVD W or electroplated Cu
u
s
e
d
Comment: typically electroplated Cu
Comment: typically electroplated Cu
Slide from Yole Developpement, Lyon
37
Different TSV Geometries
•Cylindrical vias, larger than 3 µm in diameter are usually filled with
electroplated Cu
•Tungsten cannot be used beyond due to stress concentrations.
•Cu has high thermal stresses at silicon interface.
•Polymer insulation often used
•Annular TSV geometries are becoming popular, especially with tungsten filling.
•Small volume can be filled quickly and there is redundancy
•Reduced thermal stress around vias compared to cylindrical vias.
•Thin multi-plate-like W vias are studied by IBM and they have improved current
carrying characteristics compared to annular vias and provide redundancy.
Cu vias with polymer
dielectric from IMEC
Top view
Plate-like and annular W vias
from IBM
High AR W and larger Cu vias from IZM
High-Energy Physics and TSV’s
•TSV development work is done parallel with via middle and via last technologies
within HEP community .
•Via last processes can be demonstrated with existing wafers if the designs are
compatible with it.
•Development work done in several European R&D institutes using via-last TSV
technology:
•IMEC (Timepix chips)
•IZM (FE-I3 chips)
• VTT (Medipix3)
•CEA Leti has an interesting TSV process technology - no known connections to HEP
•Via first/middle technologies would lead to ultimate goal (3D IC), but will the
technology be available for small volume products for affordable prices?
•3D IC consortium (many institutes in HEP field) using Tezzaron process for making viamiddle TSVs and wafer bonding.
•After via middle TSV’s will become commercially available, the readout chip designs
will go through a major change (signals taken out over the whole chip area – not only
via chip perimeter?)
39
High-Energy Physics and TSV’s cont’d
Vias last issues:
•At CERN we want to build TSV’s on real CMOS wafers
•Difficult processing through dielectric layer stacks before
reaching metal 1 (picture)
•Processing is expensive outside IC foundry!
•Poor electrical yields to begin with!
•Real wafers are too expensive to be wasted for TSV process
Source: IMEC, Timepix chip
development purposes.
Vias last advantages:
•Processing can be done right now
•Flexibility
•Vias middle issues:
•Completed design tools are not available yet.
•Maybe on workstations in 2012
•Many design iterations will be needed – very complex designs.
•HEP community is only at in beginning of the learning curve
Vias middle advantages:
•Potentially: cost-efficient, enhanced electrical performance, highvolume capability, high density interconnections, etc…
40
Outstanding Issues Related to TSV’s at the Moment
•TSV’s should be taken into account in design phase – new chip designs which
should be supported by the IC foundry and packaging house.
•Lack of design tools, rules and experience – adaptation to 3D thinking.
•No I/O standardization yet – no design rules for vias.
•New testing scenarios needed – no more probing pads
•Impossible to test TSVs separately
•Thermal management issues – heat generation, thermal stresses etc.
41
TSV PROTOTYPING WORK WITHIN HEP
COMMUNITY
42
Work Done Within HEP - VTT
•VTT is working with Medipix3 wafers to develop a via last process
•Tapered (86˚) vias to be produced
•conventional PVD tools can be used for processing
•Tapered angle facilitates conformal insulation and seeding
•Via etch-stop landing pads have been designed on Medipix3 wafers
•Stack of dielectrics has to be penetrated before reaching metal1.
Near the top
Insulation/ Seed layer
Near the sidewall
TEOS oxide / Cu seed
Philippe Monnoyer
At the via bottom
[email protected]
43
Work Done Within HEP - VTT
•Partial via filling process will be used in prototyping phase of Medipix3
•10 µm Cu liner
•Development of completely filled vias will follow the partial filling
•Easier and faster processing, lower thermal stresses and lower mass.
•Less issues at early stages of process development
•Thinning of wafers to 100 µm.
•Redistribution process and solderable pads
•≈ 100 BGA joints (solder will be brought come from carrier board side)
Partially filled TSV’s and a carrier wafer
wafer
Philippe Monnoyer
4:1 AR tapered via
[email protected]
44
Work Done Within HEP - IMEC
Piet De Moor, VIPS 2010 Workshop
45
Work Done Within HEP - IMEC
Piet De Moor, VIPS 2010 Workshop
46
Work Done Within HEP – IZM Berlin
Oswin Ehrmann, VIPS 2010 Workshop
47
Work Done Within HEP – IZM Berlin
Oswin Ehrmann, VIPS 2010 Workshop
48
Work Done Within HEP – 3D IC Consortium
49
Work Done Within HEP – 3D IC Consortium
50
SUMMARY
51
Summary
•Steps towards the complete 3D integration of pixel detectors were shown.
•It’s not all about making TSV’s
•TSV’s needed for readout chips.
•TSV processes are still in prototyping or R&D phase and not commercially available.
•Commercially available high density TSV processes will lead to new ROC designs.
•It is very important to use edgeless sensors in large area tiling of the detectors
•Typical structures of edgeless sensors were shown
•Improved fill factor
•Lower resistivity silicon (≈ 1 kΩcm) could be used with thinner sensor chips.
•Sensors available in 200 µm wafers?
•Chip to wafer bonding process will become popular with pixel chips.
•Better yields than in wafer bonding
•Examples on TSV processes were given within HEP community.
•Significant technical and economical challenges remain before 3D integration of
detectors realize with good yields.
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THANK YOU FOR YOUR ATTENTION
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BACKUP
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