Transcript Design Objective

TEAM W3:
Digital Voice Processor 525
Jarrett Avery (W3-1)
Sean Baker (W3-2)
Huiyi Lim (W3-3)
Sherif Morcos (W3-4)
Amar Sharma (W3-5)
Design Manager: Abhishek Jajoo
Design Goal
Design an Analog-to-Digital Conversion chip to meet
demands of high quality voice applications such as: Digital
Telephony, Digital Hearing Aids and VOIP.
Date: 2/15/2006
Gate Level Design
Status
Design Proposal
 Project chosen: 16 bit Delta-Sigma ADC
 Basic specs defined
Architecture
 Matlab Simulated
 Behavioral Verilog - Simulated
 Structural Verilog – Simulated
Schematic
 Digital – All modules created, yet to be tested
 Analog - More accurate model created
Floorplan
 Revised floorplan
Layout
 Intend to Bit Slice Sinc Filter and hopefully PII
Simulation / Verification
Algorithm Detail
Analog
Analog
Input
Analog to Digital
Conversion
Lowpass Filter
(Delta-Sigma
Modulator)
Decimation
(Sinc Filter,
Downsample)
Measure Peak
Amplitude
(Peak Input
Indicator)
Digital
Output
Digital
Peak
Indicator
Brief Analog Progress
Decided upon RC values for Low Pass
Filter
 Decided Operational Amplifier Topologies
 Modified Behavioral Schematic to more
accurately model the desired real circuit.
 Tuned the modulator
 Will all be discussed in detail Next
Week…

Algorithm Detail
Digital
Analog
Input
Analog to Digital
Conversion
Lowpass Filter
(Delta-Sigma
Modulator)
Decimation
(Sinc Filter,
Downsample)
Measure Peak
Amplitude
(Peak Input
Indicator)
Digital
Output
Digital
Peak
Indicator
Digital Design Decisions

Discovered governing formula for Digital
Resolution from Brandt and Whooley.
3
* log2 (256) = Resolution
 Changed our design from 18 bits to 24 bits.

Ran initial Schematic simulations.
Found glitches with clocking/timing. (Clk
Divider)
 Require buffering to correct.


Registered Y value coming out of the Sinc
Filter as opposed using switching.
Digital Schematic – Decimator
Overall
Hardware That Makes it Happen
(Sinc Filter)
Schematic – Sinc Filter
Hardware That Makes it Happen
(Peak Input Indicator)
Schematic - Peak Input Indicator
Hardware That Makes it Happen
(Clock Divider)
Schematic - Clock Divider
Simulation – Overall Chip
Now, we have simulated entire design in a
mixed-signal environment
 Analog portion represented by realistic
behavioral components
 Digital portion represented by Structural
Verilog code
 Simulated together in Cadence using
AHDL

Old Simulation – Overall Chip
New Simulation – Overall Chip
Digital Simulation
Simulated behavioral and structural
models of Decimator (Sinc Filter, PII
function & Clock Divider) in ModelSim
 Verified generation of Nyquist clock by
clock divider module
 Verified updates of maximum & minimum
values of sinc filter output by PII function
module

Digital Simulation Results
Revised Transistor Count

Analog



Digital










3 x Analog Op Amps, 3 x 24 = 72
Resistive/Capacitive Elements
8 x 24-bit registers, 8 x 530 = 4240
1 x 12-bit register, 1 x 260 = 260
8 x 24-bit adders, 8 x 680 = 5440
1 x 24-bit counter, 1 x 870 = 870
1 x 7-bit counter, 1 x 250 = 250
1 x 12-bit equality function, 1 x 120 = 120
2 x 24-bit muxes, 2 x 150 = 300
Misc logic/Buffers = 500
Total = 11,980 transistors
Old Total = 9,300 Transistors
Initial Floorplan
Total Area =
77, 750 sq μm
Revised Floorplan
REVISED FLOORPLAN
350 microns
Modulator
Sinc 3 Filter
1BIT
PII Function
72 Large
Transistors
900 = square
290 microns
microns
24 Bits
RC
Components
Area =
1800 =
square microns
59,147 square microns
24 Bits
Area =
7075 Transistors
41,005 square microns
4905 Transistors
Estimated
Area
Total Area = 102,852 sq μm
24 Bits PII
Total Area = 102,852 square microns
8.36 square microns per
transistor was used as an
estimate
Revised Power Consumption
We’ll be using 1.8V source
 Estimate chip’s total power ~3 mW


Digital Portion – .256 uW
= C * V2 * f
 Power = 5 MHz * (1.8 V)2 * 3.16 pF
 Capacitance Estimated from previous projects
(based on 322)
P

Analog Portion – 2.5 mW
P
= IV
 3 Op Amps * (150uA * 1.8 V) = 2.5 mW
Problems and Questions

Even More Transistors
~12,000 transistors is a lot for 3 digital
designers
 A lot of repetition
 Can always reduce design (PII function, clock
divider)


Analog RC Components
Keep them on chip?
 Outsource the analog low pass filter due to
size constraints.

Results

More comfortable with overall design





Gate level Design Completed
Structural Verilog simulations
Overall schematic including both analog & digital
portions of design
Topology, RLC selection for analog parts (next week)
Coming up Next:



Schematic Simulation
Layout
Gate Sizing - Analog