Transcript sdram

AKT211 – CAO
07 – Computer Memory
Ghifar
Parahyangan Catholic University
Okt 24, 2011
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Outline
 Computer Memory System
 Memory Characteristics
 Memory Hierarchy
 RAM Basic Technology
 Semiconductor
 SRAM vs DRAM
 Advanced RAM Organization
 SDRAM vs DDR-RAM
COMPUTER MEMORY SYSTEM
Characteristics
Location
• CPU
• Internal
• External
Capacity
• Word size
– The natural unit of organization
• Number of words
– or Bytes
Unit of Transfer
• Internal
– Usually governed by data bus width
• External
– Usually a block which is much
larger than a word
• Addressable unit
– Smallest location which can be
uniquely addressed
– Word internally
– Cluster on M$ disks
Access Methods (1)
• Sequential
– Start at the beginning and read through
in order
– Access time depends on location of data
and previous location
– e.g. tape
• Direct
– Individual blocks have unique address
– Access is by jumping to vicinity plus
sequential search
– Access time depends on location and
previous location
– e.g. disk
Access Methods (2)
• Random
– Individual addresses identify locations
exactly
– Access time is independent of location or
previous access
– e.g. RAM
• Associative
– Data is located by a comparison with
contents of a portion of the store
– Access time is independent of location or
previous access
– e.g. cache
Memory Hierarchy
 Registers
– In CPU
 Internal or Main memory
– May include one or more levels of
cache
– “RAM”
 External memory
– Backing store
Memory Hierarchy - Diagram
RAM BASIC TECHNOLOGY
Semiconductor Main Memory
• universally used as RAM basic
technology
• The basic element : “memory cell”
• Read/Write
• Volatile
• Temporary storage
• Static or dynamic
Memory Cell Operation
Semiconductor Memory Types
Dynamic RAM
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Bits stored as charge in capacitors
Charges leak
Need refreshing even when powered
Simpler construction
Smaller per bit
Less expensive
Need refresh circuits
Slower
Main memory
Essentially analogue
– Level of charge determines value
Dynamic RAM Structure
• Address line active when bit read
or written
– Transistor switch closed (current
flows)
• Write
– Voltage to bit line
• High for 1 low for 0
– Then signal address line
• Transfers charge to capacitor
• Read
– Address line selected
• transistor turns on
– Charge from capacitor fed via bit line
to sense amplifier
• Compares with reference value to
determine 0 or 1
– Capacitor charge must be restored
Static RAM
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Bits stored as on/off switches
No charges to leak
No refreshing needed when powered
More complex construction
Larger per bit
More expensive
Does not need refresh circuits
Faster
Cache
Digital
– Uses flip-flops
Static RAM Structure
SRAM v DRAM
• Both volatile
– Power needed to preserve data
• Dynamic cell
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Simpler to build, smaller
More dense
Less expensive
Needs refresh
Larger memory units
• Static
– Faster
– Cache
ADVANCED RAM ORGANIZATION
Synchronous DRAM (SDRAM)
• Access is synchronized with an external clock
– Conventional DRAM is asynchronous, CPU must wait the
access time delay
– With SDRAM, CPU doesn’t have to wait, it can do
something else
• Takes advantage of the burst mode concept to
greatly improve performance
– staying on the row containing the requested bit and
moving rapidly through the columns, reading each bits as
it goes
– Idea : most of the time the data needed by the CPU will
be in sequence !
• Maximum transfer rate to L2 cache : 528 MBps
SDRAM - Diagram
SDRAM Read Timing
DDR-SDRAM
• Double Data Rate Synchronous Dynamic
RAM
• Higher bandwidth => greater speed
• Higher transfer rate
– Uses double pumping  transferring data on both
the rising and falling edges of the clock signal
• Classes : DDR1, DDR2, DDR3
– Neither of which are either forward or backward
compatible !
DDR SDRAM
Read Timing
DDR SDRAM
Read Timing
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