Transcript Lecture19

Lecture 19
OUTLINE
The MOSFET:
• Structure and operation
• Qualitative theory of operation
• Field-effect mobility
• Body bias effect
Reading: Pierret 17.1, 18.3.4; Hu 6.1-6.5
Invention of the Field-Effect Transistor
O. Heil, British Patent 439,457 (1935)
In 1935, a British patent was issued to Oskar Heil.
A working MOSFET was not demonstrated until 1955.
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Lecture 19, Slide 2
Metal Oxide Semiconductor
Field Effect Transistor (MOSFET)
• An electric field is applied normal to the surface of the
semiconductor (by applying a voltage to an overlying electrode), to
modulate the conductance of the semiconductor.
 Drift current flowing between 2 doped regions (“source” & “drain”)
is modulated by varying the voltage on the “gate” electrode.
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Lecture 19, Slide 3
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.1
Modern MOSFETs
Metal-Oxide-Semiconductor
Field-Effect Transistor:
GATE LENGTH, Lg
OXIDE THICKNESS, xo
Intel’s 32nm CMOSFETs
Gate
Desired characteristics:
• High ON current
• Low OFF current
Source
Drain
Substrate
P. Packan et al., IEDM Technical Digest, pp. 659-662, 2009
• “N-channel” & “P-channel” MOSFETs operate
in a complementary manner
“CMOS” = Complementary MOS
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Lecture 19, Slide 4
CURRENT
• Current flowing between the SOURCE and DRAIN is controlled
by the voltage on the GATE electrode
VT
|GATE VOLTAGE|
4
N-channel vs. P-channel
NMOS
PMOS
N+ poly-Si
N+
N+
P+ poly-Si
P+
p-type Si
P+
n-type Si
• For current to flow, VGS > VT
• For current to flow, VGS < VT
to form n-type channel at surface
to form p-type channel at surface
• Enhancement mode: VT > 0
• Enhancement mode: VT < 0
• Depletion mode: VT < 0
• Depletion mode: VT > 0
Transistor is ON when VG=0V
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Lecture 19, Slide 5
Transistor is ON when VG=0V
Enhancement Mode vs. Depletion Mode
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 18.18
Enhancement Mode
Depletion Mode
Conduction between source
and drain regions is enhanced
by applying a gate voltage
A gate voltage must be applied
to deplete the channel region
in order to turn off the transistor
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Lecture 19, Slide 6
CMOS Devices and Circuits
CIRCUIT SYMBOLS
N-channel
MOSFET
P-channel
MOSFET
CMOS INVERTER CIRCUIT
VOUT
VDD
S
INVERTER
LOGIC SYMBOL
VDD
D
VIN
D
GND
VOUT
S
0
VDD
VIN
• When VG = VDD , the NMOSFET is on and the PMOSFET is off.
• When VG = 0, the PMOSFET is on and the NMOSFET is off.
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Lecture 19, Slide 7
“Pull-Down” and “Pull-Up” Devices
• In CMOS logic gates, NMOSFETs are used to connect
the output to GND, whereas PMOSFETs are used to
connect the output to VDD.
– An NMOSFET functions as a pull-down device when it is
turned on (gate voltage = VDD)
– A PMOSFET functions as a pull-up device when it is turned
on (gate voltage = GND)
VDD
input signals
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A1
A2
AN
Pull-up
network
A1
A2
AN
Pull-down
network
PMOSFETs only
F(A1, A2, …, AN)
Lecture 19, Slide 8
NMOSFETs only
CMOS NAND Gate
VDD
A
A
0
0
1
1
B
F
A
B
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Lecture 19, Slide 9
B
0
1
0
1
F
1
1
1
0
CMOS NOR Gate
VDD
A
0
0
1
1
A
B
F
B
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A
Lecture 19, Slide 10
B
0
1
0
1
F
1
0
0
0
CMOS Pass Gate
A
Y
X
A
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Lecture 19, Slide 11
Y = X if A
Qualitative Theory of the NMOSFET
VGS < VT :
depletion layer
The potential barrier to electron flow from the source
into the channel region is lowered by applying VGS> VT Inversion-layer
“channel” is formed
VGS > VT :
Electrons flow from the
source to the drain by drift,
when VDS>0. (IDS > 0)
VDS  0
The channel potential
varies from VS at the source
end to VD at the drain end.
VDS > 0
EE130/230A Fall 2013
Lecture 19, Slide 12
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.2
MOSFET Linear Region of Operation
For small values of VDS (i.e. for VDS << VGVT),
I DS  WQinvv  WQ inv m eff

 VDS 
 WQ inv m eff 

 L 
where meff is the effective carrier mobility
Hence the NMOSFET can be modeled as a resistor:
RDS
VDS
L


I DS Wmeff Coxe (VG  VT )
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Lecture 19, Slide 13
Field-Effect Mobility, meff
Scattering mechanisms:
• Coulombic scattering
• phonon scattering
• surface roughness
scattering
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Lecture 19, Slide 14
C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 6-9
MOSFET Saturation Region of Operation
VDS = VGS-VT
• When VD is increased to be equal
to VG-VT, the inversion-layer
charge density at the drain end
of the channel equals 0, i.e. the
channel becomes “pinched off”
VDS > VGS-VT
ID
I Dsat  I DS V
• As VD is increased above VG-VT,
the length DL of the “pinch-off”
region increases. The voltage
applied across the inversion layer
is always VDsat=VGS-VT, and so the
current saturates.
DS VDsa t
VDS
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Lecture 19, Slide 15
R. F. Pierret, Semiconductor Device Fundamentals, Figs. 17.2, 17-3
Ideal NMOSFET I-V Characteristics
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Lecture 19, Slide 16
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.4
Channel Length Modulation
• As VDS is increased above VDsat, the width DL of the depletion
region between the pinch-off point and the drain increases,
i.e. the inversion layer length decreases.
If DL is significant compared to L,
then IDS will increase slightly with
increasing VDS>VDsat, due to
“channel-length modulation”
I Dsat 
IDS
1
1  DL 
 1 

L  DL L 
L 
DL  VDS  VDsat
DL
  VDS  VDsat 
L
VDS
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Lecture 19, Slide 17
I Dsat  I Dsat0 1   VDS  VDsat 
R. F. Pierret, Semiconductor Device Fundamentals, Figs. 17.2, 17-3
Body Bias
• When a MOS device is biased into inversion, a pn junction
exists between the surface and the bulk.
• If the inversion layer contacts a heavily doped region of the
same type, it is possible to apply a bias to this pn junction.
N+ poly-Si
+ + + + + + + +
SiO2
N+
- - - - - - - - -
p-type Si
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• VG is biased so that surface is inverted
• n-type inversion layer is contacted by N+
region
• If a bias VC is applied to the channel, a
reverse bias (VB-VC) is applied between
the channel and body
Lecture 19, Slide 18
Effect of VCB on fS, W and VT
• Application of a reverse body bias  non-equilibrium
 2 Fermi levels (one in n-type region, one in p-type region)
are separated by qVBC  fS is increased by VCB
• Reverse body bias widens W, increases Qdep and hence VT
2qN A Si (2fF  VCB ( y))
VT ( y)  VFB  VCB ( y)  2fF 
Cox
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Lecture 19, Slide 19