Transcript Fremtidsperspektiver for UiO

PPrinsipp for transistor
iD = (15 V)/(1000 Ω) =15 mA
”load line”
iD = (0 V)/(1000 Ω) = 0
Figure 6–2 A three-terminal nonlinear device that can be controlled by the voltage at the third terminal vG: (a)
biasing circuit; (b) I–V characteristic and load line. If VG = 0.5 V, the d-c values of ID and VD are as shown by the
dashed lines.
Solid State Electronic Devices, 7e, Global Edition
Ben G. Streetman | Sanjay Kumar Banerjee
Copyright © Pearson Education Limited 2016.
All rights reserved.
JFET (Junction Field Effect Transistor)
Figure 6–4 Depletion regions in the channel of a JFET with zero gate bias for several values of VD: (a) linear
range; (b) near pinch-off; (c) beyond pinch-off.
Solid State Electronic Devices, 7e, Global Edition
Ben G. Streetman | Sanjay Kumar Banerjee
Copyright © Pearson Education Limited 2016.
All rights reserved.
Figure 6–5 Effects of a negative gate bias: (a) increase of depletion region widths with VG negative; (b) family
of current–voltage curves for the channels as VG is varied.
Solid State Electronic Devices, 7e, Global Edition
Ben G. Streetman | Sanjay Kumar Banerjee
Copyright © Pearson Education Limited 2016.
All rights reserved.
Figure 6-6 Simplified diagram of the channel with definitions of dimensions and differential volume for
calculations.
Solid State Electronic Devices, 7e, Global Edition
Ben G. Streetman | Sanjay Kumar Banerjee
Copyright © Pearson Education Limited 2016.
All rights reserved.
MESFET (Metal Semiconductor Field Effect Transistor)
Figure 6–7 GaAs MESFET formed on an n-type GaAs layer grown epitaxially on a semi-insulating substrate.
Common metals for the Schottky gate in GaAs are AI or alloys of Ti, W, and Au. The ohmic source and drain
contacts may be an alloy of Au and Ge. In this example the device is isolated from others on the same chip by
etching through the n region to the semi-insulating substrate.
Solid State Electronic Devices, 7e, Global Edition
Ben G. Streetman | Sanjay Kumar Banerjee
Copyright © Pearson Education Limited 2016.
All rights reserved.
MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
MOSFET
Ulike typer
av MOSFET
V=0
V>0
Deplesjon
av hull
Likevekt
V<0
Ansamling
av hull
V>>0
Ansamling
av elektroner
Qm = | Qd + Qn |
V = VG = Vi + Φs
C-V for n-kanal MOS-kapasitanse
(~100 Hz)
(~106 Hz)
Figure 6.16: Capacitance-voltage relation for a n-channel (p-substrate) MOS capacitor. The
dashed curve for V > VT occurs for high measurement frequencies.
Terskelspenning VT i virkeligheten; m  s
Figure 6–18 Effect of a negative work function difference (Φms < 0): (a) band bending and formation of
negative charge at the semiconductor surface; (b) achievement of the flat band condition by application of a
negative voltage.
m < s
Solid State Electronic Devices, 7e, Global Edition
Ben G. Streetman | Sanjay Kumar Banerjee
Copyright © Pearson Education Limited 2016.
All rights reserved.
Figure 6–17 Variation of the metal–semiconductor work function potential difference Φms with substrate doping
concentration, for n+ poly-Si.
Solid State Electronic Devices, 7e, Global Edition
Ben G. Streetman | Sanjay Kumar Banerjee
Copyright © Pearson Education Limited 2016.
All rights reserved.
Figure 6–19 Effects of charges in the oxide and at the interface: (a) definitions of charge densities (C/cm2)
due to various sources; (b) representing these charges as an equivalent sheet of positive charge Qi at the
oxide–semiconductor interface. This positive charge induces an equivalent negative charge in the
semiconductor, which requires a negative gate voltage to achieve the flat band condition.
VT i virkeligheten; positive
ladninger i gate-oksiden
Solid State Electronic Devices, 7e, Global Edition
Ben G. Streetman | Sanjay Kumar Banerjee
Copyright © Pearson Education Limited 2016.
All rights reserved.
Ei∞
qΦ(x) = Ei∞ - Ei(x)
VT i virkeligheten
Figure 6.20
Influence of materials
parameters on threshold
voltage.
(a) the threshold voltage
equation indicating signs
of the four contributions.
(b) variation of VT with
substrate doping for nchannel and p-channel
n+ poly-SiO2-Si devices.
VT år 1990 vs 2010
1990
1990
2010
Al-SiO2-Si devices
n+ poly-SiO2-Si devices
y(x)
Innvirken av elektriskt felt (Ex og Ey) på kanalmobilitet
Sammenlikning av likning 6:49 og 6:50
8.0
N-MOSFET
L = 1 µm
Z = 10 µm
d(SiO2) = 10 nm
7.0
6.0
VG = 3 V
Na = 1x1015 cm-3
VT = 0.54 V
5.0
Eq. (6:49)
4.0
Eq. (6:50)
3.0
VG = 2 V
2.0
1.0
0.0
0.0
0.4
0.8
1.2
1.6
V D (Volt)
2.0
2.4
2.8
’Typical feature size’ vs tid for Si-DRAM (Moore’s lov)
Figure 9.3