Transcript PPT - the GMU ECE Department

ECE 448
Lecture 7
FPGA Devices
& FPGA Design Flow
George Mason University
Required reading
• P. Chu, RTL Hardware Design using VHDL
Chapter 1, Introduction to Digital System Design
• Spartan-6 FPGA CLB, User Guide


CLB Overview
Slice Description
2
Two competing implementation approaches
ASIC
Application Specific
Integrated Circuit
FPGA
Field Programmable
Gate Array
• designed all the way
from behavioral description
to physical layout
• no physical layout design;
design ends with
a bitstream used
to configure a device
• designs must be sent
for expensive and time
consuming fabrication
in semiconductor foundry
• bought off the shelf
and reconfigured by
designers themselves
3
Which Way to Go?
ASICs
FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes
Reconfigurability
4
What is an FPGA?
Configurable
Logic
Blocks
Block RAMs
Block RAMs
I/O
Blocks
Block
RAMs
5
Modern FPGA
RAM blocks
RAM
blocks
Multipliers
Multipliers/DSP
units
Logic
blocks
Logic
resources
(#Logic resources, #Multipliers/DSP units, #RAM_blocks)
Graphics based on The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
6
Major FPGA Vendors
SRAM-based FPGAs
• Xilinx, Inc.
~ 51% of the market
• Altera Corp. ~ 34% of the market
• Lattice Semiconductor
• Atmel
~ 85%
Flash & antifuse FPGAs
• Actel Corp. (Microsemi SoC Products Group)
• Quick Logic Corp.
7
Xilinx

Primary products: FPGAs and the associated CAD
software
Programmable
Logic Devices


ISE Alliance and Foundation
Series Design Software
Main headquarters in San Jose, CA
Fabless* Semiconductor and Software Company




UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}
Seiko Epson (Japan)
TSMC (Taiwan)
Samsung (Korea)
8
Xilinx FPGA Families
Technology
220 nm
180 nm
Low-cost
Spartan II,
Spartan IIE
120/150 nm
90 nm
65 nm
45 nm
40 nm
28 nm
Highperformance
Virtex
Spartan 3
Virtex II,
Virtex II Pro
Virtex 4
Virtex 5
Spartan 6
Artix 7
Virtex 6
Virtex 7
Altera FPGA Families
Technology
Low-cost
Mid-range
Highperformance
130 nm
Cyclone
Stratix
90 nm
Cyclone II
Stratix II
65 nm
Cyclone III
Arria I
Stratix III
40 nm
Cyclone IV
Arria II
Stratix IV
28 nm
Cyclone V
Arria V
Stratix V
FPGA Family
11
Spartan 6 FPGA Family
12
CLB Structure
George Mason University
General structure of an FPGA
Programmable
interconnect
Programmable
logic blocks
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
14
Xilinx Spartan 6 CLB
15
Row & Column Relationship Between
CLBs & Slices
16
Three Different Types of Slices
50%
25%
25%
17
SLICEX
18
SLICEL
19
Xilinx Multipurpose LUT (MLUT)
16-bit
SR
32-bit SR
16
64xx11 RAM
RAM
4-input
LUT
64 x 1 ROM
(logic)
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
20
4-input LUT (Look-Up Table) in the Basic
ROM Mode
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x1
x2
x3
x4
y
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
LUT
y
x1 x2 x3 x4
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
y
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
• Look-Up tables
are primary
elements for
logic
implementation
• Each LUT can
implement any
function of
4 inputs
x1 x2
y
y
21
6-Input LUT of Spartan 6
22
23
Reset and Set Configurations
•
•
•
•
•
No set or reset
Synchronous set
Synchronous reset
Asynchronous set (preset)
Asynchronous reset (clear)
24
MLUT as a 32-bit Shift Register (SRL32)
25
Fast Carry Logic
Each CLB contains separate
logic and routing for the fast
generation of sum & carry
signals
MSB
Carry Logic
Routing

• Increases efficiency and
performance of adders,
subtractors, accumulators,
comparators, and counters

Carry logic is independent of
normal logic and routing
resources
LSB
26
Accessing Carry Logic

All major synthesis tools can infer carry
logic for arithmetic functions
•
•
•
•
Addition (SUM <= A + B)
Subtraction (DIFF <= A - B)
Comparators (if A < B then…)
Counters (count <= count +1)
27
Full-adder
cout
FA
s
2
x
y
cin
1
x + y + cin = ( cout s )2
x
0
0
0
0
1
1
1
1
y
0
0
1
1
0
0
1
1
cin cout
0 0
1 0
0 0
1 1
0 0
1 1
0 1
1 1
s
0
1
1
0
1
0
0
1
Carry & Control Logic in Xilinx FPGAs
x
0
0
1
1
y COUT
0 y
1 CIN
0 CIN
1 y
x
y
Propagate = x  y
Generate = y
Sum= Propagate  CIN = x  y  CIN
Carry & Control Logic in Spartan 6 FPGAs
x
y
LUT
Hardwired (fast) logic
Examples:
Determine the amount of
Spartan 6 resources needed
to implement a given circuit
George Mason University
Circuit 1:
Top level
m
0
w
1
run
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
clk
a
b
c
d
F
y
Circuit 1:
F – function
a
b
a
b
c
d
y3
w1
y2
w0
y1
En
y0
2-to-4 Decoder
a
x3
y3
b
x2
y2
<<<3
c
x1
y1
d
x0
y0
e
0
1
2
3
4
5
6
7
1
e
1
0
f
y
0
3
f
g
s
h
cout
Full
Adder
cin
x
y
g
h
c
d
Circuit 2:
Top level
0
z
1
run
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
clk
a
b
c
d
e
F
y
Circuit 2:
F – function
a
e
a
w3
y1
b
w2
y0
c
w1
z
d
w0 Encoder
Priority
a
b
c
x3
y3
x2
y2 g
x1
y1 h
>>2
d
x0
y0
f
0
1
2
3
4
5
6
7
1
g
1
0
h
y
0
3
s
i
cout
Half
Adder
x
y
e
i
Circuit 3: Top level
Input/Output Blocks
(IOBs)
George Mason University
Basic I/O Block Structure
D Q
EC
Three-State
FF Enable
Clock
SR
Three-State
Control
Set/Reset
D Q
EC
Output
FF Enable
Output Path
SR
Direct Input
FF Enable
Registered
Input
Q
D
EC
Input Path
SR
39
IOB Functionality
• IOB provides interface between the
package pins and CLBs
• Each IOB can work as uni- or bi-directional
I/O
• Outputs can be forced into High Impedance
• Inputs and outputs can be registered
• advised for high-performance I/O
• Inputs can be delayed
40
Clock Management
George Mason University
A simple clock tree
Clock
tree
Flip-flops
Special clock
pin and pad
Clock signal from
outside world
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
42
Clock Manager
Clock signal from
outside world
Clock
Manager
etc.
Daughter clocks
used to drive
internal clock trees
or output pins
Special clock
pin and pad
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
43
Jitter
1
2
3
4
Ideal clock signal
Real clock signal with jitter
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Superimposed cycles
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
44
Removing Jitter
Clock signal from
outside world
with jitter
Clock
Manager
etc.
“Clean” daughter
clocks used to drive
internal clock trees
or output pins
Special clock
pin and pad
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
45
Frequency Synthesis
1.0 x original clock frequency
2.0 x original clock frequency
.5 x original clock frequency
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
46
Phase shifting
0o Phase shifted
90o Phase shifted
180o Phase shifted
270o Phase shifted
Figure 4-20
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
47
Clock Management Tiles
DCM – Digital Clock Manager
PLL - Phase Locked Loop
48
Spartan-6 Family Attributes
George Mason University
Spartan-6 FPGA Family Members
50
FPGA device present on the
Digilent Nexys 3 board
XC6SLX16-CSG324C
Spartan 6
family
Size
Logic
Optimized
324 pins
Package type
(Ball Chip-Scale)
Commercial
temperature range
0° C – 85° C
51
FPGA Design Flow
George Mason University
FPGA Design process (1)
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds…..
Specification / Pseudocode
On-paper hardware design
(Block diagram & ASM chart)
VHDL description (Your Source Files)
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Functional simulation
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;
Synthesis
Post-synthesis simulation
FPGA Design process (2)
Implementation
Timing simulation
Configuration
On chip testing
Tools used in FPGA Design Flow
Functionally
verified
VHDL code
Design
VHDL code
Xilinx XST
Synplify Premier
Synthesis
Netlist
Xilinx ISE
Implementation
Bitstream
55
Synthesis
George Mason University
Synthesis Tools
Xilinx XST
Synplify Premier
… and others
57
Logic Synthesis
VHDL description
Circuit netlist
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;
MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;
with (L1 & L0) select
Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;
58
Circuit netlist (RTL view)
59
Mapping
LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
60
Xilinx XST Inputs/Outputs
61
Xilinx XST Inputs
• RTL VHDL and/or Verilog files
• Constraints – XCF
Xilinx constraints file in which you can specify
synthesis, timing, and specific implementation
constraints that can be propagated to the NGC file.
• Core files
These files can be in either NGC or EDIF format.
XST does not modify cores. It uses them to inform
area and timing optimization surrounding the cores.
62
Xilinx XST Outputs
• NGC
Netlist file with constraint information
• NGR
This is a schematic representation of the pre-optimized
design shown at the Register Transfer Level (RTL).
This representation is in terms of generic symbols,
such as adders, multipliers, counters, AND gates, and
OR gates, and is generated after the HDL synthesis phase
of the synthesis process.
• LOG
This report contains the results from the synthesis run,
including area and timing estimation.
63
RTL view in Synplify Premier
General logic structures can be recognized in RTL view
comparator
incrementer
MUX
Crossprobing between RTL view and code
Each port, net or block can be chosen by mouse click from the
browser or directly from the RTL View
By double-clicking on the element its source code can be seen:
Reverse crossprobing is also possible: if section of code is marked,
appropriate element of RTL View is marked too:
Technology View in Synplify Pro
Technology view is a mapped RTL view. It can be seen by pressing
button
or by double-click on “.srm” file
As in case of “RTL View”, buttons
can be used here
Two additional buttons are enabled:
Pay attention:
technology view
is usually large
and presented on
number of sheets
Ports, nets and
blocks browser
- show critical path
- open timing analyst
Technology view is
presented using device
primitives
Viewing critical path
Critical path can be viewed by pressing on
Delay values are written near each component of the path
Implementation
George Mason University
Implementation
• After synthesis the entire implementation
process is performed by FPGA vendor
tools
69
Implementation
70
Translation
Synthesis
Circuit
Netlist
Timing
Constraints
Constraint Editor
or Text Editor
UCF
User Constraint File
Translation
NGD
Native Generic Database file
71
Mapping
LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
72
Placing
FPGA
CLB SLICES
73
Routing
FPGA
Programmable Connections
74
Configuration
• Once a design is implemented, you must create a
file that the FPGA can understand
• This file is called a bit stream: a BIT file (.bit extension)
• The BIT file can be downloaded directly to the
FPGA, or can be converted into a PROM file
which stores the programming information
75
Two main stages of the
FPGA Design Flow
Implementation
Synthesis
Technology
dependent
Technology
independent
RTL
Synthesis
- Code analysis
- Derivation of main logic
constructions
- Technology independent
optimization
- Creation of “RTL View”
Map
Place & Route
- Mapping of extracted logic
structures to device primitives
- Technology dependent
optimization
- Application of “synthesis
constraints”
-Netlist generation
- Creation of “Technology View”
Configure
- Placement of generated
netlist onto the device
-Choosing best interconnect
structure for the placed
design
-Application of “physical
constraints”
- Bitstream
generation
- Burning device
Synthesis Report Example –
Resource Utilization (1)
Device utilization summary:
--------------------------Selected Device : 6slx4tqg144-3
Slice Logic Utilization:
Number of Slice Registers:
Number of Slice LUTs:
Number used as Logic:
Slice Logic Distribution:
Number of LUT Flip Flop pairs used:
Number with an unused Flip Flop:
Number with an unused LUT:
Number of fully used LUT-FF pairs:
Number of unique control sets:
53 out of 4800
163 out of 2400
163 out of 2400
198
145 out of 198
35 out of 198
18 out of 198
7
1%
6%
6%
73%
17%
9%
77
Synthesis Report Example –
Resource Utilization (2)
IO Utilization:
Number of IOs:
Number of bonded IOBs:
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs:
Number of DSP48A1s:
43
43 out of
102
42%
1 out of 16 6%
5 out of
8 62%
78
Synthesis Report Example –
Timing
Timing Summary:
--------------Speed Grade: -3
Minimum period: 6.031ns (Maximum Frequency: 165.817MHz)
79
Map Report Example –
Resource Utilization (1)
Design Summary
-------------Slice Logic Utilization:
Number of Slice Registers:
54 out of
Number used as Flip Flops:
53
Number used as Latches:
0
Number used as Latch-thrus:
0
Number used as AND/OR logics:
1
Number of Slice LUTs:
149 out of
Number used as logic:
148 out of
Number using O6 output only:
133
Number using O5 output only:
0
Number using O5 and O6:
15
Number used as ROM:
0
Number used as Memory:
0 out of
Number used exclusively as route-thrus:
1
4,800
1%
2,400 6%
2,400 6%
1,200
0%
80
Map Report Example –
Resource Utilization (2)
Slice Logic Distribution:
Number of occupied Slices:
Number of MUXCYs used:
Number of LUT Flip Flop pairs used:
Number with an unused Flip Flop:
Number with an unused LUT:
Number of fully used LUT-FF pairs:
Number of unique control sets:
Number of slice register sites lost
to control set restrictions:
IO Utilization:
Number of bonded IOBs:
58 out of
32 out of
162
109 out of
13 out of
40 out of
7
600
1,200
162 67%
162 8%
162 24%
35 out of 4,800
43 out of
9%
2%
1%
102 42%
81
Map Report Example –
Resource Utilization (3)
Specific Feature Utilization:
Number of RAMB16BWERs:
Number of RAMB8BWERs:
…….
Number of DSP48A1s:
…….
0 out of
0 out of
5 out of
12
24
0%
0%
8 62%
82
Post-PAR Static Timing Report
Clock to Setup on destination clock clk_i
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock
|Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_i
|
7.530|
|
|
|
---------------+---------+---------+---------+---------+
83
PAR Report
---------------------------------------------------------------------------------------------------------Constraint
|
Check
| Worst Case | Best Case | Timing |
Timing
|
|
Slack
| Achievable | Errors |
Score
---------------------------------------------------------------------------------------------------------Autotimespec constraint for clock net clk | SETUP
|
N/A|
7.530ns|
N/A|
0
_i_BUFGP
| HOLD
|
0.457ns|
|
0|
0
----------------------------------------------------------------------------------------------------------
84
Timing Report (1)
Timing constraint: Default period analysis for net "clk_i_BUFGP"
3354 paths analyzed, 309 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 7.530ns.
-------------------------------------------------------------------------------Delay (setup path): 7.530ns (data path - clock path skew + uncertainty)
Source:
a_register/q_o_4 (FF)
Destination:
x_reg_inst/q_o_3 (FF)
Data Path Delay:
7.453ns (Levels of Logic = 2)
Clock Path Skew:
-0.042ns (0.513 - 0.555)
Source Clock:
clk_i_BUFGP rising
Destination Clock: clk_i_BUFGP rising
Clock Uncertainty: 0.035ns
85
Timing Report (2)
Maximum Data Path at Slow Process Corner: a_register/q_o_4 to x_reg_inst/q_o_3
Location
Delay type
Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- ------------------SLICE_X4Y36.AQ
Tcko
0.447
a_register/q_o<4>
a_register/q_o_4
DSP48_X0Y3.B4
net (fanout=21)
1.194
a_register/q_o<4>
DSP48_X0Y3.M3
Tdspdo_B_M
3.364
Mmult_mult_unsigned
Mmult_mult_unsigned
SLICE_X8Y39.C4
net (fanout=1)
2.050
mult_unsigned<3>
SLICE_X8Y39.CLK
Tas
0.398
x_reg_inst/q_o<3>
Mmux_x_57
Mmux_x_4_f7_2
Mmux_x_2_f8_2
x_reg_inst/q_o_3
------------------------------------------------- -------------------Total
7.453ns (4.209ns logic,
3.244ns route)
(56.5% logic, 43.5% route)
86
Timing Report (3)
-------------------------------------------------------------------------------Delay (setup path): 7.484ns (data path - clock path skew + uncertainty)
Source:
a_register/q_o_7_1 (FF)
Destination:
x_reg_inst/q_o_3 (FF)
Data Path Delay: 7.391ns (Levels of Logic = 2)
Clock Path Skew: -0.058ns (0.513 - 0.571)
Source Clock:
clk_i_BUFGP rising
Destination Clock: clk_i_BUFGP rising
Clock Uncertainty: 0.035ns
Clock Uncertainty:
0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ):
0.000ns
Discrete Jitter (DJ):
0.000ns
Phase Error (PE):
0.000ns
87
Timing Report (4)
Maximum Data Path at Slow Process Corner: a_register/q_o_7_1 to
x_reg_inst/q_o_3
Location
Delay type
Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- ------------------SLICE_X2Y33.AQ
Tcko
0.447
a_register/q_o_7_2
a_register/q_o_7_1
DSP48_X0Y3.B7
net (fanout=13)
1.132
a_register/q_o_7_1
DSP48_X0Y3.M3
Tdspdo_B_M
3.364
Mmult_mult_unsigned
Mmult_mult_unsigned
SLICE_X8Y39.C4
net (fanout=1)
2.050
mult_unsigned<3>
SLICE_X8Y39.CLK
Tas
0.398
x_reg_inst/q_o<3>
Mmux_x_57
Mmux_x_4_f7_2
Mmux_x_2_f8_2
x_reg_inst/q_o_3
------------------------------------------------- -------------------Total
7.391ns (4.209ns logic,
3.182ns route)
(56.9% logic, 43.1% route)
88
Xilinx FPGA Memories
Recommended reading
• Spartan-6 FPGA Block RAM Resources: User Guide
Google search: UG383
• Spartan-6 FPGA Configurable Logic Block: User Guide
Google search: UG384
• Xilinx FPGA Embedded Memory Advantages: White Paper
Google search: WP360
• ISE In-Depth Tutorial, Section: Creating a CORE Generator Tool Module
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90
Memory Types
91
Memory Types
Memory
RAM
ROM
Memory
Single port
Dual port
Memory
With asynchronous
read
With synchronous
read
92
Memory Types specific to Xilinx FPGAs
Memory
Distributed
(MLUT-based)
Block RAM-based
(BRAM-based)
Memory
Inferred
Instantiated
Manually
Using CORE
Generator
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CORE Generator
CORE Generator
FPGA Distributed
Memory
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Location of Distributed RAM
Logic resources
(CLB slices)
RAM blocks
RAM
blocks
Multipliers
DSP units
Logic
blocks
Logic
resources
(#Logic resources, #Multipliers/DSP units, #RAM_blocks)
Graphics based on The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
97
Three Different Types of Slices
50%
25%
25%
98
Spartan-6 Multipurpose LUT (MLUT)
16-bit
SR
32-bit SR
16
64xx11 RAM
RAM
4-input
LUT
64 x 1 ROM
(logic)
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
99
Single-port 64 x 1-bit RAM
100
Memories Built of Neighboring MLUTs
Memories built of 2 MLUTs:
• Single-port 128 x 1-bit RAM:
• Dual-port
64 x 1-bit RAM :
RAM128x1S
RAM64x1D
Memories built of 4 MLUTs:
•
•
•
•
Single-port 256 x 1-bit RAM:
RAM256x1S
Dual-port 128 x 1-bit RAM:
RAM128x1D
Quad-port 64 x 1-bit RAM:
RAM64x1Q
Simple-dual-port 64 x 3-bit RAM:
RAM64x3SDP
(one address for read, one address for write)
101
Dual-port 64 x 1 RAM
•
•
Dual-port 64 x 1-bit RAM :
Single-port 128 x 1-bit RAM:
ECE 448 – FPGA and ASIC Design with VHDL
64x1D
128x1S
102
Total Size of Distributed RAM
103
FPGA Block RAM
104
Location of Block RAMs
Logic resources
(CLB slices)
RAM blocks
RAM
blocks
Multipliers
DSP units
Logic
blocks
Logic
resources
(#Logic resources, #Multipliers/DSP units, #RAM_blocks)
Graphics based on The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
105
Spartan-6 Block RAM Amounts
106
Block RAM can have various configurations (port
aspect ratios)
1
2
0
4
0
0
4k x 4
8k x 2
4,095
16k x 1
8,191
8+1
0
2k x (8+1)
2047
16+2
0
1023
1024 x (16+2)
16,383
107
108
109
Block RAM Port Aspect Ratios
110
Block RAM Interface
111
Block RAM Ports
112
Block RAM with synchronous read
in Read-First Mode
EN
CE
113
Features of Block RAMs in Spartan-6 FPGAs
114